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1. WO2020117193 - CIRCUITS LOGIQUES

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CLAIMS

1. A logic circuitry package having a first address and comprising a first logic circuit, wherein the first address is an I2C address for the first logic circuit, and wherein the package is configured such that, in response to a first command indicative of a task and a first time period sent to the first address, the first logic circuit is to, for a duration of the time period:

(i) perform a task, and

(ii) disregard I2C traffic sent to the first address.

2. The logic circuitry package of Claim 1 wherein the first logic circuit further comprises a timer to measure the time period.

3. A logic circuitry package according to Claim 2 wherein the task performed by the logic circuitry package comprises at least one of: monitoring the timer and performing a computational task having a completion time which exceeds the time period.

4. A logic circuitry package according to any preceding Claim wherein the package is for association with a print material container.

5. A logic circuitry package according to Claim 4 further comprising a memory storing data representative of at least one characteristic of the print material container.

6. A logic circuitry package according to any preceding Claim wherein the package comprises a second logic circuit and the package is configured to make the second logic circuit accessible during the time period.

7. A logic circuitry package according to Claim 6 wherein the package comprises a dedicated signal path between the first and second logic circuit and the second logic circuit is made accessible by the first logic circuit sending a signal via the dedicated signal path.

8. A logic circuitry package according to Claim 7 wherein the signal is present for the duration of the time period.

9. A logic circuitry package according to any preceding Claim which comprises at least one sensor or sensor array.

10. A logic circuitry package according to Claim 9 wherein the at least one sensor comprises at least one print material level sensor.

1 1 . A logic circuitry package according to any preceding Claim wherein the package has at least one second address and is configured such that, in response to the first command, the package is accessible via a second address for the duration of the time period.

12. A logic circuitry package according to Claim 1 1 wherein the package is configured to provide a first set of responses in response to instructions sent to the first address and to provide a second set of responses in response to instructions sent to a second address.

13. A logic circuitry package according to Claim 1 1 or Claim 12 wherein the package is configured to operate in a first mode in response to instructions sent to the first address and to operate in a second mode in response to instructions sent to the second address.

14. A logic circuitry package according to any of Claims 1 1 to 13 wherein the package is configured to provide a cryptographically authenticated set of responses in response to cryptographically authenticated communications sent to the first address and to provide a second, not cryptographically authenticated, set of responses in response to

communications sent to the second address.

15. A logic circuitry package according to any of Claims 1 1 to 14 which is configured to transmit, outside of said time period and in response to communications sent to the first address, print material level-related data that is authenticated using an encryption key, and which is further configured to transmit, during the time period and in response to

communications sent to the second address, print material level-related data not authenticated using that key.

16. A logic circuitry package according to any of Claims 1 1 to 15 wherein the at least one second address is an address of a second logic circuit.

17. A logic circuitry package according to any of Claims 1 1 to 16 wherein the package is not accessible via the second address for a second time period preceding the first time period and/or for a third time period following the first time period.

18. A logic circuitry package according to any of Claims 1 1 to 17 configured to set the second address to an initial second address at each start of the first time period.

19. A logic circuitry package according to Claim 18 wherein the package is configured to set its second address to a temporary address in response to a command sent to the initial second address, the command including that temporary address.

20. A logic circuitry package according to Claim 18 or 19, wherein, on receipt of a subsequent command indicative of a task and the first time period sent to the first address, the logic circuitry package is configured to have the same initial second address.

21 . A logic circuitry package according to any of Claims 1 1 to 20 which is configured to: respond to commands directed to the first address and not to commands directed to the second address outside the first time period; and

respond to commands directed to the second address and not to commands directed to the first address during the first time period.

22. A plurality of logic circuitry packages according to any of Claims 11 to 21 having different first addresses and the same second address.

23. A method comprising:

in response to a first command indicative of a task and a first time period sent to a first address of processing circuitry via an I2C bus

(0 performing, by the processing circuitry, a task and

(=0 disregarding I2C traffic sent to the first address

for a duration of the time period, the method comprising monitoring the time period using a timer of the processing circuitry.

24. A method according to Claim 23 wherein the method is carried out on processing circuitry provided on a replaceable print apparatus component.

25. A method according to any of Claims 23 to 24, further comprising, for the duration of the time period, responding, by the processing circuitry, to I2C traffic sent to at least one second address of the processing circuitry.

26. A method according to Claim 25 wherein the first address is associated with a first logic circuit of the processing circuitry, and the at least one second address is associated with a second logic circuit of the processing circuitry.

27. A method according to Claim 25 or 26 further comprising disabling access to the processing circuitry via the at least one second address after the duration of the time period.

28. A method according to any of Claims 25 to 27 wherein the second address is configured to be an initial second address at the start of the first time period.

29. A method according to Claim 28 wherein the processing circuitry is configured to reconfigure its second address to a temporary second address in response to a command sent to the initial second address and including that temporary address during the first time period.

30. A method according to Claim 29, wherein, on receipt of a subsequent command indicative of the task and the first time period sent to the first address, the logic circuitry is configured to have the same initial second address.

31 . A method according to any of Claims 23 to 30 wherein the processing circuitry comprises a first logic circuit and a second logic circuit of the processing circuitry, wherein the first logic circuit is to perform the task and to send an activation signal to the second logic circuit for the duration of the time period.

32. A method according to Claim 31 wherein the method further comprises deactivating the second logic circuit by ceasing the activation signal.

33. A method according to Claim 31 or 32 wherein the activation signal is sent via a dedicated signal path.

34. A method according to any of Claims 23 to 33 wherein the task performed by the processing circuitry is the task indicated in the first command.

35. Processing circuitry for use with a replaceable print apparatus component to connect to a print apparatus logic circuit comprising:

a memory and first logic circuit to enable a read operation from the memory and perform processing tasks, the first logic circuit comprising a timer,

wherein the processing circuitry is accessible via an I2C bus of a print apparatus in which the replaceable print apparatus component is installed and is associated with a first address and at least one second address, and the first address is an I2C address for the first logic circuit, and

wherein the first logic circuit is to participate in authentication of the replaceable print apparatus component by a print apparatus in which the replaceable print apparatus component is installed; and

the processing circuitry is configured such that, in response to a first command indicative of a task and a first time period sent to the first logic circuit via the first address, the processing circuitry is to:

(i) perform a task, and

(ii) not respond to I2C traffic sent to the first address

for a duration of the time period as measured by the timer.

36. Processing circuitry according to Claim 35 wherein the processing circuitry further comprises a second logic circuit, wherein the second logic circuit is accessible via the I2C

bus and a second address, and the first logic circuit is to generate an activation signal to activate the second logic circuit for the duration of the time period.

37. Processing circuitry according to Claim 36 wherein the processing circuitry comprises a dedicated signal path between the first and second logic circuits for transmitting the activation signal.

38. Processing circuitry according to Claim 36 or 37 wherein the second logic circuit comprises at least one sensor which is readable by a print apparatus in which the replaceable print apparatus component is installed via the second address.

39. Processing circuitry according to any of Claims 36 to 38 comprising at least one sensor which is readable by a print apparatus in which the replaceable print apparatus component is installed via the second address and which is not readable via the first address.

40. Processing circuitry according to Claim 38 or 39 wherein the sensor comprises a consumable materials level sensor.

41 . A plurality of print components each comprising a memory, wherein the memories of different print component store different print liquid characteristics, and each print component comprises a logic circuitry package according to any of Claims 1 to 21 or processing circuitry of Claims 35 to 40.

42. A print cartridge comprising a logic circuitry package according to any of Claims 1 to 21 and having a housing that has a width that is less than a height, wherein, in a front face, from bottom to top, a print liquid output, an air input and a recess are provided, respectively, the recess extending at the top, wherein I2C bus contacts of the package are provided at a side of the recess against an inner side of a side wall of the housing adjacent the top and front of the housing, and comprise a data contact, the data contact being the lowest of the I2C bus contacts.

43. A print cartridge according to Claim 42, wherein the first logic circuit of the package is also provided against the inner side of the side wall.

44. A replaceable print apparatus component including the logic circuitry package of any of Claims 1 to 21 , the component further comprising a volume of liquid, the component having a height that is greater than a width and a length that is greater than the height, the width extending between two sides, wherein the package comprises interface pads, and the interface pads are provided at an inner side of one of the sides facing a cut-out for a data interconnect to be inserted, the interface pads extending along a height direction near the top and front of the component, and a data pad is a bottom-most of the interface pads, the liquid and air interface of the component being provided at the front on the same vertical reference axis parallel to the height direction wherein the vertical axis is parallel to and distanced from the axis that intersects the interface pads.

45. A replaceable print apparatus component according to Claim 44 wherein the rest of the logic circuitry package is also provided against the inner side.