Traitement en cours

Veuillez attendre...

Paramétrages

Paramétrages

Aller à Demande

1. WO2020113578 - NOUVEAU DISPOSITIF DE MÉMOIRE NON-ET 3D ET PROCÉDÉ DE FORMATION ASSOCIÉ

Numéro de publication WO/2020/113578
Date de publication 11.06.2020
N° de la demande internationale PCT/CN2018/119908
Date du dépôt international 07.12.2018
CIB
H01L 27/24 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
27Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun
24comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
CPC
G11C 16/0483
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0483comprising cells having several storage transistors connected in series
G11C 16/14
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
14Circuits for erasing electrically, e.g. erase voltage switching circuits
H01L 21/0276
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
0271comprising organic layers
0273characterised by the treatment of photoresist layers
0274Photolithographic processes
0276using an anti-reflective coating
H01L 21/31116
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31105Etching inorganic layers
31111by chemical means
31116by dry-etching
H01L 21/31144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31144using masks
H01L 23/528
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528Geometry or; layout of the interconnection structure
Déposants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventeurs
  • SONG, Yali
  • XIAO, Lihong
  • WANG, Ming
Mandataires
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Données relatives à la priorité
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) NOVEL 3D NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME
(FR) NOUVEAU DISPOSITIF DE MÉMOIRE NON-ET 3D ET PROCÉDÉ DE FORMATION ASSOCIÉ
Abrégé
(EN)
A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.
(FR)
L'invention concerne un dispositif de mémoire NON-ET 3D. Le dispositif de mémoire selon l'invention comprend un substrat, une grille de sélection inférieure (BSG) disposée sur le substrat, une pluralité de lignes de mots placées sur la BSG avec une configuration en escalier, et une pluralité de couches isolantes disposées entre le substrat, la BSG et la pluralité de lignes de mots. Dans le dispositif de mémoire selon l'invention, au moins une première tranchée diélectrique est formée dans la BSG et s'étend dans le sens de la longueur du substrat afin de diviser la BSG en une pluralité de sous-BSG. En outre, au moins une région source commune est formée sur le substrat et s'étend dans le sens de la longueur du substrat. Ladite région source commune au moins s'étend également sur la BSG, la pluralité de lignes de mots et la pluralité de couches isolantes.
Également publié en tant que
CN201880002892.5
Dernières données bibliographiques dont dispose le Bureau international