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1. WO2020068121 - CIRCUIT DE MESURE DE CHARGE DE MEMRISTOR

Numéro de publication WO/2020/068121
Date de publication 02.04.2020
N° de la demande internationale PCT/US2018/053461
Date du dépôt international 28.09.2018
CIB
G01R 31/26 2006.01
GPHYSIQUE
01MÉTROLOGIE; TESTS
RMESURE DES VARIABLES ÉLECTRIQUES; MESURE DES VARIABLES MAGNÉTIQUES
31Dispositions pour tester les propriétés électriques; Dispositions pour la localisation des pannes électriques; Dispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
26Test de dispositifs individuels à semi-conducteurs
CPC
G01R 31/2637
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
26Testing of individual semiconductor devices
2607Circuits therefor
2637for testing other individual devices
G01R 31/50
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
G11C 2029/5004
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
50Marginal testing, e.g. race, voltage or current testing
5004Voltage
G11C 29/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
G11C 29/12005
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
12005comprising voltage or current generators
G11C 29/50008
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
50Marginal testing, e.g. race, voltage or current testing
50008of impedance
Déposants
  • HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP [US]/[US]
Inventeurs
  • BUCHANAN, Brent
  • ZHENG, Le
  • STRACHAN, John Paul
Mandataires
  • VELEZ, Santiago
  • DRYJA, Michael A.
Données relatives à la priorité
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) CHARGE METERING CIRCUIT FOR MEMRISTOR
(FR) CIRCUIT DE MESURE DE CHARGE DE MEMRISTOR
Abrégé
(EN)
A charge metering circuit for a memristor includes a switch connected between a stimulus voltage and the memristor. The switch is pulsed on to apply the stimulus voltage to the memristor. The circuit includes a current mirror connected between a low-rail voltage and the memristor and having a primary leg and a secondary leg, and a capacitor connected between a capacitor voltage and the secondary leg. The primary leg pulls a voltage at the memristor to a virtual ground voltage upon pulsing on of the switch, and the secondary leg pulls a current through the capacitor from the capacitor voltage.
(FR)
L'invention concerne un circuit de mesure de charge d'un memristor comprenant un commutateur connecté entre une tension de stimulus et le memristor. Le commutateur est pulsé afin d'appliquer la tension de stimulus au memristor. Le circuit comprend un miroir de courant connecté entre une tension de rail bas et le memristor et comprenant une branche primaire et une branche secondaire, et un condensateur connecté entre une tension de condensateur et la branche secondaire. La branche primaire tire une tension au niveau du memristor vers une tension de masse virtuelle lors de l'impulsion sur le commutateur, et la branche secondaire tire un courant à travers le condensateur à partir de la tension de condensateur.
Dernières données bibliographiques dont dispose le Bureau international