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1. WO2020023743 - CIRCUIT INTÉGRÉ DOTÉ D'UNE RÉSISTANCE À FILM MINCE À PAROIS MÉTALLIQUES

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[ EN ]

CLAIMS

1. A method of fabricating an integrated circuit (IC), comprising:

providing a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer;

forming a thin film resistor (TFR) comprising a TFR layer on the ILD layer;

forming at least one vertical metal wall on at least two sides of the TFR;

wherein the metal walls include at least 2 metal levels coupled by filled vias, and wherein the functional circuitry is outside the metal walls.

2. The method of claim 1, wherein the TFR layer comprises silicon chromium (SiCr) or nickel chromium (NiCr).

3. The method of claim 2, wherein the TFR layer comprises doped polysilicon.

4. The method of claim 1, wherein a thickness of the TFR layer is 1 nm to 100 nm.

5. The method of claim 1, further comprising laser trimming the TFR.

6. The method of claim 1, wherein the metal walls each include at least 2 of the metal walls.

7. The method of claim 1, wherein the at least 2 metal levels of the metal walls include a staggered plurality of metal islands.

8. The method of claim 1, wherein the at least 2 metal levels of the metal walls share a minimum width on the IC.

9. The method of claim 1, wherein the metal walls are electrically isolated from the semiconductor surface layer.

10. The method of claim 1, wherein the TFR has a sheet resistance of 100 to 1,000 ohms/square.

11. An integrated circuit (IC), comprising:

a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer;

a thin film resistor (TFR) comprising a TFR layer on the ILD layer, and

at least one vertical metal wall on at least two sides of the TFR,

wherein the metal walls include at least 2 metal levels coupled by filled vias, and wherein the functional circuitry is outside the metal walls.

12. The IC of claim 11, wherein the TFR layer comprises silicon chromium (SiCr) or nickel chromium (NiCr).

13. The IC of claim 11, wherein the TFR layer comprises doped polysilicon.

14. The IC of claim 11, wherein a thickness of the TFR layer is 1 nm to 100 nm.

15. The IC of claim 11, wherein the metal walls each include at least 2 of the metal walls.

16. The IC of claim 11, wherein the at least 2 metal levels of the metal walls include a staggered plurality of metal islands.

17. The IC of claim 11, wherein the at least 2 metal levels of the metal walls share a minimum width on the IC.

18. The IC of claim 11, wherein the metal walls are electrically isolated from the semiconductor surface layer.

19. The IC of claim 11, wherein the TFR has a sheet resistance of 100 to 1,000 ohms/square.

20. The IC of claim 11, wherein the IC comprises an analog IC.