Traitement en cours

Veuillez attendre...

Paramétrages

Paramétrages

Aller à Demande

1. WO2019055970 - TRAITEMENTS POUR TROUS D'INTERCONNEXION AUTO-ALIGNÉS SÉLECTIVEMENT GRAVÉS

Numéro de publication WO/2019/055970
Date de publication 21.03.2019
N° de la demande internationale PCT/US2018/051469
Date du dépôt international 18.09.2018
CIB
H01L 21/768 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
70Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun, ou de parties constitutives spécifiques de ceux-ci; Fabrication de dispositifs à circuit intégré ou de parties constitutives spécifiques de ceux-ci
71Fabrication de parties spécifiques de dispositifs définis en H01L21/7089
768Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
CPC
H01L 21/0271
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
0271comprising organic layers
H01L 21/0337
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
033comprising inorganic layers
0334characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
0337characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
H01L 21/31116
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31105Etching inorganic layers
31111by chemical means
31116by dry-etching
H01L 21/32136
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
321After treatment
3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
32133by chemical means only
32135by vapour etching only
32136using plasmas
H01L 21/76811
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76807for dual damascene structures
76811involving multiple stacked pre-patterned masks
H01L 21/76813
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76807for dual damascene structures
76813involving a partial via etch
Déposants
  • APPLIED MATERIALS, INC. [US]/[US]
Inventeurs
  • LIN, Yung-Chen
  • ZHOU, Kevin
  • ZHANG, Ying
  • HWANG, Ho-yung
Mandataires
  • MCCORMICK, Daniel K.
  • BERNARD, Eugene J.
Données relatives à la priorité
62/560,09318.09.2017US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) SELECTIVELY ETCHED SELF-ALIGNED VIA PROCESSES
(FR) TRAITEMENTS POUR TROUS D'INTERCONNEXION AUTO-ALIGNÉS SÉLECTIVEMENT GRAVÉS
Abrégé
(EN)
Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively recessing a first metal on a semiconductor substrate with respect to an exposed first dielectric material. The methods may include forming a liner over the recessed first metal and the exposed first dielectric material. The methods may include forming a second dielectric material over the liner. The methods may include forming a hard mask over selected regions of the second dielectric material. The methods may also include selectively removing the second dielectric material to expose a portion of the liner overlying the recessed first metal.
(FR)
Cette invention concerne des procédés de traitement qui peuvent être réalisés pour exposer une région de contact sur un substrat semi-conducteur. Les procédés peuvent consister à évider sélectivement un premier métal sur un substrat semi-conducteur par rapport à un premier matériau diélectrique exposé. Les procédés peuvent consister à former un revêtement sur le premier métal en retrait et le premier matériau diélectrique exposé. Les procédés peuvent consister à former un second matériau diélectrique sur le revêtement. Les procédés peuvent consister à former un masque dur sur des régions sélectionnées du second matériau diélectrique. Les procédés peuvent également consister à éliminer sélectivement le second matériau diélectrique pour exposer une partie du revêtement recouvrant le premier métal en retrait.
Également publié en tant que
Dernières données bibliographiques dont dispose le Bureau international