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1. (WO2019005087) SUPPRESSION DE FUITE DE COURANT DANS DES DISPOSITIFS FINFET DE TYPE N
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

Claims:

1. A transistor channel layer arrangement, comprising:

a semiconductor layer for an N-type metal-oxide-semiconductor (NMOS) field-effect transistor (FinFET), the semiconductor layer having a plurality of regions with different dopant concentrations, the plurality of regions comprising:

an N-well region comprising one or more N-type regions,

a P-well region,

a low-doped buffer region between the P-well region and the N-well region, the low-doped buffer region comprising P-type dopants with a dopant concentration less than that of the P-well region, and

a connection region over the low-doped buffer region, between the P-well region and the N-well region, the connection region comprising N-type dopants.

2. The transistor channel layer arrangement according to claim 1, wherein the one or more N-type regions include a highly doped (HD) drain region and a shallow implant between the connection region and the HD drain region.

3. The transistor channel layer arrangement according to claim 2, wherein a dopant concentration of the shallow implant is higher than a dopant concentration of the connection region.

4. The transistor channel layer arrangement according to claim 2, wherein a dopant concentration of the shallow implant is lower than a dopant concentration of the HD drain region.

5. The transistor channel layer arrangement according to any one of claims 2-4, wherein a first portion of the shallow implant region is in contact with a portion of the connection region or wherein a second portion of the shallow implant region is in contact with a portion of the HD drain region.

6. The transistor channel layer arrangement according to claim 1, wherein the plurality of regions further includes:

a dopant diffusion blocking region between the low-doped buffer region and the connection region, the dopant diffusion blocking region comprising P-type dopants.

7. The transistor channel layer arrangement according to claim 6, wherein at least a portion an uppermost side of the dopant diffusion blocking region is in contact with a portion of the connection region.

8. The transistor channel layer arrangement according to claim 6, wherein at least a portion a lowermost side of the dopant diffusion blocking region is in contact with a portion of the low-doped buffer region.

9. The transistor channel layer arrangement according to claim 6, wherein the dopant diffusion blocking region is between the P-well region and the N-well region.

10. The transistor channel layer arrangement according to claim 6, wherein a dopant concentration of the dopant diffusion blocking region is higher than a dopant concentration of the low-doped buffer region.

11. The transistor channel layer arrangement according to claim 6, wherein a dopant concentration of the dopant diffusion blocking region is lower than a dopant concentration of the P-well region.

12. The transistor channel layer arrangement according to any one of claims 6-11, wherein the one or more N-type regions include a highly doped (HD) drain region, and a shallow implant between the connection region and the HD drain region.

13. The transistor channel layer arrangement according to claim 12, wherein the semiconductor layer is shaped as a fin, the fin comprising an active fin portion and a sub-fin portion.

14. The transistor channel layer arrangement according to claim 13, wherein a thickness of the shallow implant is between 5% and 100% of a height of the active fin portion of the fin.

15. The transistor channel layer arrangement according to claim 13, wherein a thickness of the connection region is between 5% and 100% of a height of the active fin portion of the fin.

16. The transistor channel layer arrangement according to claim 13, wherein a thickness of the dopant diffusion blocking region is between 5% and 100% of a height of the active fin portion of the fin.

17. The transistor channel layer arrangement according to claim 13, wherein a thickness of the connection region is between 5% and 100% of a height of the active fin portion of the fin.

18. The transistor channel layer arrangement according to any one of claims 1-4 or 6-11, wherein the connection region is an uppermost layer in the semiconductor layer.

19. A method of manufacturing a transistor structure, the method comprising:

providing a semiconductor layer comprising one or more semiconductor materials and having a plurality of regions with different dopant concentrations, the plurality of regions comprising:

an N-well region comprising one or more N-type regions,

a P-well region,

a low-doped buffer region between the P-well region and the N-well region, the low-doped buffer region comprising P-type dopants with a dopant concentration less than that of the P-well region, and

a connection region over the low-doped buffer region, between the P-well region and the N-well region, the connection region comprising N-type dopants;

providing a gate electrode stack over a first portion of the semiconductor layer; and

providing a source electrode and a drain electrode over portions of the semiconductor layer on different sides of the gate electrode stack.

20. The method according to claim 19, wherein providing the plurality of regions with different dopant concentrations comprises performing ion dopant implantation on the one or more semiconductor materials of the semiconductor layer.

21. The method according to claim 19, wherein providing the plurality of regions with different dopant concentrations comprises:

forming one or more openings in the one or more semiconductor materials of the semiconductor layer, and

depositing one or more doped semiconductor materials into the one or more openings to form the plurality of regions with different dopant concentrations.

22. A transistor structure comprising:

a semiconductor layer comprising one or more semiconductor materials and having a plurality of regions with different dopant concentrations, the plurality of regions comprising:

an N-well region comprising one or more N-type regions, the one or more N-type regions comprising a highly doped (HD) drain region,

a P-well region,

a low-doped buffer region between the P-well region and the N-well region, the low-doped buffer region comprising P-type dopants with a dopant concentration less than that of the P-well region, and

a connection region over the low-doped buffer region, between the P-well region and the N-well region, the connection region comprising N-type dopants;

a drain electrode over the HD drain region; and

a gate electrode stack over a portion of the semiconductor layer that is not adjacent to the HD drain region.

23. The transistor structure according to claim 22, wherein the portion of the semiconductor layer under the gate electrode stack comprises a portion of the connection region.

24. The transistor structure according to claim 22, wherein the portion of the semiconductor layer under the gate electrode stack is in contact with a portion of the connection region.

25. The transistor structure according to any one of claims 22-24, wherein the plurality of regions further comprises a HD source region, and the transistor structure further comprises a source electrode over the HD source region, wherein at least a portion of the HD source region is in contact with the P-well region.