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1. WO2015095394 - CONTACTS ALLONGÉS UTILISANT UN PROCÉDÉ DE LITHO-GEL, LITHO-GRAVURE

Numéro de publication WO/2015/095394
Date de publication 25.06.2015
N° de la demande internationale PCT/US2014/070954
Date du dépôt international 17.12.2014
CIB
H01L 21/8249 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
70Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun, ou de parties constitutives spécifiques de ceux-ci; Fabrication de dispositifs à circuit intégré ou de parties constitutives spécifiques de ceux-ci
77Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun
78avec une division ultérieure du substrat en plusieurs dispositifs individuels
82pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
822le substrat étant un semi-conducteur, en utilisant une technologie au silicium
8248Combinaison de technologie bipolaire et de technologie à effet de champ
8249Technologie bipolaire et MOS
CPC
H01L 21/0273
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
0271comprising organic layers
0273characterised by the treatment of photoresist layers
H01L 21/0274
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
0271comprising organic layers
0273characterised by the treatment of photoresist layers
0274Photolithographic processes
H01L 21/31116
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31105Etching inorganic layers
31111by chemical means
31116by dry-etching
H01L 21/31144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31144using masks
H01L 21/762
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
762Dielectric regions ; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
H01L 21/76802
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
Déposants
  • TEXAS INSTRUMENTS INCORPORATED [US]/[US]
  • TEXAS INSTRUMENTS JAPAN LIMITED [JP]/[JP] (JP)
Inventeurs
  • BLATCHFORD, James, Walter
  • JESSEN, Scott, William
Mandataires
  • DAVIS, Jr., Michael, A.
Données relatives à la priorité
61/916,85117.12.2013US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS
(FR) CONTACTS ALLONGÉS UTILISANT UN PROCÉDÉ DE LITHO-GEL, LITHO-GRAVURE
Abrégé
(EN)
In described examples, a process forms an integrated circuit (1000) containing: elongated contacts (1034) that connect to three active areas (1002) and/or MOS gates (1012); and elongated contacts that connect to two active areas (1002) and/or MOS gates (1012) and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask.
(FR)
On décrit, dans des exemples, un procédé de fabrication d'un circuit intégré (1000) comprenant: des contacts allongés (1034) qui se connectent à trois zones actives (1002) et/ou à des grilles MOS (1012); et des contacts allongés qui se connectent à deux zones actives (1002) et/ou à des grilles MOS (1012) et se connectent directement à un premier niveau d'interconnexion, par un un procédé de litho-gel, litho-gravure, pour un masque de gravure de contact.
Également publié en tant que
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