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1. WO2014099406 - ENSEMBLE CIRCUIT INTÉGRÉ EMPILÉ DOS À DOS ET PROCÉDÉ DE RÉALISATION

Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

[ EN ]

What is claimed is:

1. An integrated circuit assembly comprising:

a first substrate having a first surface and a second surface,

a first active layer formed on the first surface of the first substrate, the first active layer including a first metal bond pad;

a second substrate having a first surface and a second surface, the second surface of the first substrate being coupled to the second surface of the second substrate, and

a second active layer formed on the first surface of the second substrate, the second active layer including a second metal bond pad.

2. The assembly of claim 1 , wherein the second substrate is less than 30 microns thick.

3. The assembly of claim 1 , wherein the second substrate is less than 10 microns thick.

4. The assembly of claim 1 , wherein the first substrate and the second substrate are each less than or equal to 100 microns thick.

5. The assembly of claim 1 , wherein the first active layer or the second active layer includes passive devices.

6. The assembly of claim 1 , further comprising:

a printed circuit board, the printed circuit board being electrically connected to the first active layer and the second active layer.

7. The assembly of claim 6, wherein the printed circuit board is electrically connected with a solder bump to the first active layer

8. The assembly of claim 6 wherein the printed circuit board is electrically connected to the second active layer through a wire bond.

9. The assembly of claim 1 , further comprising an insulating layer interposed between the second surface of the first substrate and the second surface of the second substrate.

10. The assembly of claim 1 , wherein the second substrate is insulating.

1 1. A method of forming an integrated circuit assembly, the method comprising:

providing a first substrate having a first surface and a second surface; forming a first active layer on the first surface of the first substrate;

providing a second substrate having a first surface and a second surface, wherein the second substrate includes a second active layer formed on the first surface of the second substrate; and

coupling the second surface of the second substrate to the second surface of the first substrate.

12, The method of claim 1 1 wherein the step of providing a second substrate comprises: providing a semiconductor-on-insulator including an insulating layer interposed between an active semiconductor layer and a handle layer, and

removing at least a portion of the handle layer.

13. The method of claim 12, wherein the handle layer is completely removed.

14. The method of claim 12 further comprising:

before the step of removing at least a portion of the handle layer, bonding a temporary carrier to the active semiconductor layer of the semiconductor-on-insulator; and

after the step of coupling the second surface of the second substrate to the second surface of the first substrate, removing the temporary carrier.

55. The method of claim 1 1 further comprising forming a metal bond pad on the first active layer.

16, The method of claim 1 5 further comprising forming a metal bond pad on the second active layer.

17. The method of claim 1 1 further comprising thinning the first substrate before coupling the second surface of the second substrate to the second surface of the first substrate.

18. The method of claim 1 1 wherein the first substrate is a semiconductor wafer.

19. The method of claim 18, wherein the step of forming a first active layer on the first surface of the first substrate comprises forming a complementary metal-oxide-semiconductor circuit.

20. The method of claim 1 1 , wherein the first active layer or the second active layer includes passive devices.

21. The method of claim 1 1 , further comprising:

singulating the integrated circuit assembly into individual integrated circuit chips.

22. The method of claim 1 1 , further comprising:

electrically connecting a printed circuit board to the first active layer and the second active layer.

23. The method of claim 22, wherein the step of electrically connecting a printed circuit board to the first active layer and the second active layer comprises:

forming a first metal bond pad on the first active layer;

forming a second metal bond pad on the second active layer;

forming a solder bump on the first metal bond pad on the first active layer;

attaching the solder bump to a third metal pad on the printed circuit board, and wire bonding the second metal bond pad on the second active layer to a fourth metal pad on the printed circuit board,

24. The method of claim 1 5 , wherein the step of coupling the second surface of the second substrate to the second surface of the first substrate comprises:

applying an adhesive layer to the second surface of the first substrate; and contacting the second surface of the second substrate to the adhesive layer.

25. The method of claim 1 1 , wherein the step of coupling the second surface of the second substrate to the second surface of the first substrate comprises fusion bonding.

26, The method of claim 1 5 , wherein the step of coupling the second surface of the second substrate to the second surface of the first substrate comprises aligning the second substrate to the first substrate to an accuracy of no less than 5 microns.