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1. WO2014099406 - ENSEMBLE CIRCUIT INTÉGRÉ EMPILÉ DOS À DOS ET PROCÉDÉ DE RÉALISATION

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Numéro de publication WO/2014/099406
Date de publication 26.06.2014
N° de la demande internationale PCT/US2013/073466
Date du dépôt international 06.12.2013
CIB
H01L 23/12 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
23Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
12Supports, p.ex. substrats isolants non amovibles
CPC
H01L 21/6835
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; ; Apparatus not specifically provided for elsewhere
683for supporting or gripping
6835using temporarily an auxiliary support
H01L 21/6836
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; ; Apparatus not specifically provided for elsewhere
683for supporting or gripping
6835using temporarily an auxiliary support
6836Wafer tapes, e.g. grinding or dicing support tapes
H01L 21/78
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
H01L 2221/68327
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2221Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
683for supporting or gripping
68304using temporarily an auxiliary support
68327used during dicing or grinding
H01L 2221/68381
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2221Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
683for supporting or gripping
68304using temporarily an auxiliary support
68381Details of chemical or physical process used for separating the auxiliary support from a device or wafer
H01L 2224/16145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16135the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
16145the bodies being stacked
Déposants
  • SILANNA SEMICONDUCTOR U.S.A., INC. [US]/[US]
Inventeurs
  • STUBER, Michael A.
  • MOLIN, Stuart B.
Mandataires
  • MUELLER, Heather
Données relatives à la priorité
13/725,40321.12.2012US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) BACK-TO-BACK STACKED INTEGRATED CIRCUIT ASSEMBLY AND METHOD OF MAKING
(FR) ENSEMBLE CIRCUIT INTÉGRÉ EMPILÉ DOS À DOS ET PROCÉDÉ DE RÉALISATION
front page image
Abrégé
(EN)
An integrated circuit assembly includes a first substrate and a second substrate, with active layers formed on the first surfaces of each substrate, and with the second surfaces of each substrate coupled together. A method of fabricating an integrated circuit assembly includes forming active layers on the first surfaces of each of two substrates, and coupling the second surfaces of the substrates together.
(FR)
La présente invention a trait à un ensemble circuit intégré qui comprend un premier substrat et un second substrat, des couches actives étant formées sur les premières surfaces de chaque substrat, et les secondes surfaces de chaque substrat étant couplées l'une à l'autre. La présente invention a également trait à un procédé de fabrication d'un ensemble circuit intégré qui comprend les étapes consistant à former des couches actives sur les premières surfaces de chacun des deux substrats, et à coupler les secondes surfaces des substrats.
Également publié en tant que
US20140175637
CN104871309
KR1020150099736
US20160233198
Dernières données bibliographiques dont dispose le Bureau international
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