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1. WO2012005543 - DISPOSITIF DE MÉMOIRE À SEMI-CONDUCTEURS

Numéro de publication WO/2012/005543
Date de publication 12.01.2012
N° de la demande internationale PCT/KR2011/005022
Date du dépôt international 08.07.2011
CIB
G11C 7/06 2006.01
GPHYSIQUE
11ENREGISTREMENT DE L'INFORMATION
CMÉMOIRES STATIQUES
7Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique
06Amplificateurs de lecture; Circuits associés
G11C 7/18 2006.01
GPHYSIQUE
11ENREGISTREMENT DE L'INFORMATION
CMÉMOIRES STATIQUES
7Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique
18Organisation de lignes de bits; Disposition de lignes de bits
CPC
G11C 11/4074
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4094
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4094Bit-line management or control circuits
G11C 11/4097
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4097Bit-line organisation, e.g. bit-line layout, folded bit lines
G11C 5/025
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
G11C 5/063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
G11C 7/06
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
06Sense amplifiers; Associated circuits, ; e.g. timing or triggering circuits
Déposants
  • 윤재만 YOON, Jae Man [KR/KR]; KR
Inventeurs
  • 윤재만 YOON, Jae Man; KR
Mandataires
  • 리앤목특허법인 Y.P.LEE, MOCK & PARTNERS; 서울시 서초구 서초동 1575-1 1575-1 Seocho-dong, Seocho-gu Seoul 137-875, KR
Données relatives à la priorité
10-2010-006605108.07.2010KR
10-2011-006740407.07.2011KR
Langue de publication coréen (KO)
Langue de dépôt coréen (KO)
États désignés
Titre
(EN) SEMICONDUCTOR MEMORY DEVICE
(FR) DISPOSITIF DE MÉMOIRE À SEMI-CONDUCTEURS
(KO) 반도체 메모리 장치
Abrégé
(EN)
The present invention relates to a semiconductor memory device comprising a memory cell array and at least one sense amplifier, wherein the memory cell comprises at least one word line, at least one cell bit line, and at least one memory cell disposed on a region where the at least one word line and the at least one cell bit line cross each other, and the at least one sense amplifier is disposed on or under the memory cell array so as to flatly overlap the memory cell array, is connected to at least one bit line, which is connected to the at least one cell bit line, and to at least one complementary bit line corresponding to the at least one bit line, and senses data stored in the at least one memory cell. The at least one sense amplifier comprises a voltage reducing unit which reduces a voltage of a signal having a lower voltage level between signals of the at least one bit line and the at least one complementary bit line, a voltage boosting unit which boosts a voltage of a signal having a higher voltage level between the signals of the at least one bit line and the at least one complementary bit line, and an equalizing unit which equalizes the signals of the at least one bit line and the at least one complementary bit line.
(FR)
La présente invention concerne un dispositif de mémoire à semi-conducteurs, comprenant un réseau de cellules de mémoire et au moins un amplificateur de lecture. La cellule de mémoire comprend au moins une ligne de mot et au moins une ligne de bit de cellule ; au moins une cellule de mémoire est disposée au-dessus d'une région où se croisent ladite au moins une ligne de mot et ladite au moins une ligne de bit de cellule ; et ledit au moins un amplificateur de lecture est disposé au-dessus ou au-dessous du réseau de cellules de mémoire, afin de recouvrir à plat le réseau de cellules de mémoire. Il est connecté à au moins une ligne de bit qui est connectée à ladite au moins une ligne de bit de cellule et à au moins une ligne de bit complémentaire correspondant à ladite au moins une ligne de bit et il lit des données stockées dans ladite au moins une cellule de mémoire. Ledit au moins un amplificateur de lecture comprend une unité de réduction de la tension qui réduit la tension d'un signal ayant un niveau de tension inférieur parmi les signaux de ladite au moins une ligne de bit et de ladite au moins une ligne de bit complémentaire, une unité d'amplification de tension qui amplifie la tension d'un signal ayant un niveau de tension supérieur parmi les signaux de ladite au moins une ligne de bit et de ladite au moins une ligne de bit complémentaire et une unité d'égalisation qui égalise les signaux de ladite au moins une ligne de bit et de ladite au moins une ligne de bit complémentaire.
(KO)
본 발명은 반도체 메모리 장치에 관한 것으로, 적어도 하나의 워드 라인, 적어도 하나의 셀 비트 라인, 및 적어도 하나의 워드 라인과 적어도 하나의 셀 비트 라인이 교차하는 영역에 배치되는 적어도 하나의 메모리 셀을 포함하는 메모리 셀 어레이, 및 메모리 셀 어레이와 평면적으로 중첩되도록 메모리 셀 어레이의 상부 또는 하부에 배치되고, 적어도 하나의 셀 비트 라인에 연결되는 적어도 하나의 비트 라인 및 적어도 하나의 비트 라인에 대응되는 적어도 하나의 상보 비트 라인에 연결되며, 적어도 하나의 메모리 셀에 저장된 데이터를 감지하는 적어도 하나의 센스 앰프를 포함하고, 적어도 하나의 센스 앰프는, 적어도 하나의 비트 라인의 신호 및 적어도 하나의 상보 비트 라인의 신호 중 낮은 전압 레벨을 가진 신호를 감압시키는 감압부, 적어도 하나의 비트 라인의 신호 및 적어도 하나의 상보 비트 라인의 신호 중 높은 전압 레벨을 가진 신호를 승압시키는 승압부, 및 적어도 하나의 비트 라인의 신호 및 적어도 하나의 상보 비트 라인의 신호를 등화시키는 등화부를 포함한다.
Dernières données bibliographiques dont dispose le Bureau international