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1. WO2007106635 - DISPOSITIF DE COMMUTATION ET PROCEDE ASSOCIE

Numéro de publication WO/2007/106635
Date de publication 20.09.2007
N° de la demande internationale PCT/US2007/062196
Date du dépôt international 15.02.2007
CIB
G11C 11/34 2006.01
GPHYSIQUE
11ENREGISTREMENT DE L'INFORMATION
CMÉMOIRES STATIQUES
11Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants
21utilisant des éléments électriques
34utilisant des dispositifs à semi-conducteurs
CPC
G11C 11/413
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
G11C 7/02
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
02with means for avoiding parasitic signals
H01L 27/11
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
11Static random access memory structures
H01L 27/1104
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
11Static random access memory structures
1104the load element being a MOSFET transistor
H01L 29/66795
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
66787with a gate at the side of the channel
66795with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
H01L 29/785
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
785having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Déposants
  • FREESCALE SEMICONDUCTOR INC. [US]/[US] (AllExceptUS)
  • BURNETT, James, D. [US]/[US] (UsOnly)
Inventeurs
  • BURNETT, James, D.
Mandataires
  • KING, Robert, L.
Données relatives à la priorité
11/373,53210.03.2006US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) SWITCH DEVICE AND METHOD
(FR) DISPOSITIF DE COMMUTATION ET PROCEDE ASSOCIE
Abrégé
(EN)
A device (100) is disclosed having a first Field Effect Transistor (102) having a channel region controlled by a gate (108, 110), a second Field Effect Transistor (104) having a first channel region substantially controlled by a first gate (112), and a second channel region substantially controlled by a second gate (122). The gate (108, 110) of the first Field Effect Transistor and the first gate (112) of the second Field Effect Transistor are coupled to a memory write line. The second gate (112) of the second Field Effect Transistor receives a control signal from a memory bit cell.
(FR)
L'invention concerne un dispositif (100) comprenant un premier transistor à effet de champ (102) pourvu d'une zone de canal commandée par une grille (108, 110), un deuxième transistor à effet de champ (104) pourvu d'une première zone de canal commandée sensiblement par une première grille (112) et d'une deuxième zone de canal commandée sensiblement par une deuxième grille (122). La grille (108, 110) du premier transistor à effet de champ et la première grille (112) du deuxième transistor à effet de champ sont couplées à une ligne d'écriture de mémoire. La deuxième grille (112) du deuxième transistor à effet de champ reçoit un signal de commande provenant d'une cellule de mémoire binaire.
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