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1. WO2005020080 - UNITE INTERFACE POUR BATTERIES DE CACHES

Numéro de publication WO/2005/020080
Date de publication 03.03.2005
N° de la demande internationale PCT/US2004/024911
Date du dépôt international 30.07.2004
Demande présentée en vertu du Chapitre 2 08.06.2005
CIB
G06F 12/08 2006.01
GPHYSIQUE
06CALCUL; COMPTAGE
FTRAITEMENT ÉLECTRIQUE DE DONNÉES NUMÉRIQUES
12Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
02Adressage ou affectation; Réadressage
08dans des systèmes de mémoires hiérarchiques, p.ex. des systèmes de mémoire virtuelle
CPC
G06F 12/0813
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
0813with a network or matrix configuration
G06F 12/084
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
084with a shared cache
G06F 12/0859
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0844Multiple simultaneous or quasi-simultaneous cache accessing
0855Overlapped cache accessing, e.g. pipeline
0859with reload from main memory
G06F 15/7846
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
7839with memory
7842on one IC chip (single chip microcontrollers)
7846On-chip cache and off-chip main memory
G06F 9/3824
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3824Operand accessing
G06F 9/3851
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3851from multiple instruction streams, e.g. multistreaming
Déposants
  • SUN MICROSYSTEMS, INC. [US]/[US] (AllExceptUS)
  • OLUKOTUN, Kunle, A. [US]/[US] (UsOnly)
Inventeurs
  • OLUKOTUN, Kunle, A.
Mandataires
  • GENCARELLA, Michael, L.
Données relatives à la priorité
10/855,65826.05.2004US
60/496,60219.08.2003US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) CACHE BANK INTERFACE UNIT
(FR) UNITE INTERFACE POUR BATTERIES DE CACHES
Abrégé
(EN)
A server including an application processor chip. The application processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. A plurality of cache bank memories is included. Each of the cache bank memories include a tag array region configured to store data associated with each line of the cache bank memories, a data array region configured to store the data of the cache bank memories, an access pipeline configured to handle accesses from the plurality of processing cores, and a miss handling control unit configured to control the sequencing of cache-line transfers between a corresponding cache bank memory and a main memory. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided.
(FR)
L'invention porte sur un serveur comportant une puce de traitement d'applications incluant plusieurs noyaux à files multiples et plusieurs mémoires à batteries de caches comportant chacune: une zone de réseaux de marqueurs enregistrant les données associées à chacune des lignes des mémoires; une zone de réseaux de données enregistrant les données des mémoires; un pipeline d'accès traitant les accès à partir des noyaux de traitement; et une unité de gestion des fausses manoeuvres gérant le séquençage des transferts des lignes de caches entre les mémoires à batteries de caches et la mémoire principale. Il est en outre prévu un réseau matriciel assurant les communications entre les noyaux de traitement et les mémoires à batteries de caches.
Également publié en tant que
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