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1. WO2005006423 - DEPOT AUTOCATALYTIQUE ET DEPOT PAR IMMERSION SUR CIRCUITS INTEGRES AU MOYEN D'UNE PLAQUE D'ACTIVATION

Numéro de publication WO/2005/006423
Date de publication 20.01.2005
N° de la demande internationale PCT/US2004/021062
Date du dépôt international 29.06.2004
CIB
H01L 21/302 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
02Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
04les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
18les dispositifs ayant des corps semi-conducteurs comprenant des éléments du groupe IV de la classification périodique, ou des composés AIIIBV, avec ou sans impuretés, p.ex. des matériaux de dopage
30Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes H01L21/20-H01L21/26162
302pour changer leurs caractéristiques physiques de surface ou leur forme, p.ex. gravure, polissage, découpage
CPC
C23C 18/1651
CCHEMISTRY; METALLURGY
23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
18Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
16by reduction or substitution, e.g. electroless plating
1601Process or apparatus
1633Process of electroless plating
1646Characteristics of the product obtained
165Multilayered product
1651Two or more layers only obtained by electroless plating
H01L 2224/03464
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
03Manufacturing methods
034by blanket deposition of the material of the bonding area
0346Plating
03464Electroless plating
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/04042
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
H01L 2224/05644
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05638the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
05644Gold [Au] as principal constituent
H01L 2224/45124
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
45099Material
451with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
45117the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
45124Aluminium (Al) as principal constituent
Déposants
  • FREESCALE SEMICONDUCTOR, INC. [US/US]; 6501 William Cannon Drive West Austin, TX 78735, US (AllExceptUS)
  • DEAN, Timothy, B. [US/US]; US (UsOnly)
  • LYTLE, William, H. [US/US]; US (UsOnly)
Inventeurs
  • DEAN, Timothy, B.; US
  • LYTLE, William, H.; US
Mandataires
  • KING, Robert, L.; Freescale Semiconductor, Inc. 7700 West Parmer Lane MD: PL02 Austin, TX 78729, US
Données relatives à la priorité
10/611,54601.07.2003US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) ELECTROLESS AND IMMERSION PLATING OF INTEGRATED CIRCUITS USING AN ACTIVATION PLATE
(FR) DEPOT AUTOCATALYTIQUE ET DEPOT PAR IMMERSION SUR CIRCUITS INTEGRES AU MOYEN D'UNE PLAQUE D'ACTIVATION
Abrégé
(EN)
The invention provides a method of plating an integrated circuit. An activation plate is positioned adjacent to at least one integrated circuit. The integrated circuit includes a plurality of bond pads comprising a bond-pad metal, and the activation plate also comprises the bond-pad metal. A layer of electroless nickel is plated on the bond pads and the activation plate, and a layer of gold is plated over the layer of electroless nickel on the bond pads and the activation plate. An integrated circuit with bond pads plated using the activation plate, and a system for plating an integrated circuit is also disclosed.
(FR)
L'invention concerne un procédé destiné à réaliser un dépôt sur un circuit intégré. Une plaque d'activation est disposée au voisinage d'au moins un circuit intégré. Ce circuit intégré comprend une pluralité de plots de connexion renfermant un métal de plot de connexion, la plaque d'activation comprenant également ce métal de plot de connexion. Une couche de nickel autocatalytique est déposée sur les plots de connexion et la plaque d'activation, une couche d'or étant déposée sur la couche de nickel autocatalytique sur les plots de connexion et la plaque d'activation. L'invention concerne également un circuit intégré comprenant des plots de connexion déposés au moyen de cette plaque d'activation, ainsi qu'un système destiné à réaliser un dépôt sur un circuit intégré.
Également publié en tant que
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