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1. WO2004100232 - PROCEDE DE FORMATION DE LA PLAQUE SUPERIEURE D'UN CONDENSATEUR MIM A UN SEUL MASQUE DANS UNE STRUCTURE D'INTEGRATION EN CUIVRE A DOUBLE DAMASQUINAGE

Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

[ EN ]

WHAT IS CLAIMED IS:
1. A method of fabricating a melal-insulator-metal (MIM) capacitor, the method comprising: providing a semiconductor wafer;
forming at least one first capacitor plate over the wafer;
forming a firsl insulating layer over the wafer, wherein a top surface of the al least one first capacitor plate is exposed;
selectively forming a first cap layer over die at least one first capacitor plate top surface; forming a second insulating layer over the firsl insulating layer and the first cap layer, the second insulating layer having a lop surface;
patterning the second insulating layer witii at least one second capacitor plate pattern; depositing a capacitor dielectric layer over the second insulating layer;
depositing a second capacitor plate material over the capacitor dielectric layer; and planarizing the wafer to remove the second capacitor plate material and capacitor dielechic layer from over the second insulating layer top surface and fonri at leasl one second capacitor plalc within the patterned second insulating layer, wherein the at least one second capacitor plate, capacitor dielectric layer and at least one first capacitor plate form a MIM capacitor.

2. The method according to Claim 1, further comprising depositing a dielectric cap layer over the first cap layer and first insulating layer, before forming the second insulating layer, wherein patterning die second insulating layer includes patterning the dielectric cap layer with the al least one second capacitor plalc pattern.

3. The method according lo Claim 2, wherein depositing the dielectric cap layer comprises depositing SiN, SiC, SiCN or BloK™, or a dielectric material with diffusion barrier properties againsl metal ion or metal atom diffusion.

4. The mediod according to Claim 1, further comprising selectively forming a second cap layer over Uie second capacitor plate.

5. The method according to Claim 4, wherein depositing the second capacitor plate material comprises depositing an alloy-containing seed layer over die patterned second insulatmg layer, wherein selectively fonning the second cap layer comprises passivating the top surface of the second capacitor plate material by annealing the semiconductor wafer.

6. The method according lo Claim 5, further comprising depositing a third insulating layer over at least the second insulating layer, and patterning the third insulating layer to Torni a via pattern abutting the second cap layer, wherein a portion of the second cap layer is removed when patterning die third insulating layer, further comprising annealing the semiconductor wafer to repair the removed second cap layer, after palteming the third insulating layer.

7. The mediod according to Claim 4, wherein selectively forming die second cap layer comprises selectively depositing a metallic diffusion bamer.

8. The method according to Claim 7, wherein depositing the metallic diffusion hairier comprises depositing CoWP, CoWB, CoP, NiMoP, Re or Ru.

9. The method according to Claim 7, further comprising:
recessing the second capacitor plate material below a top surface of the second insulating layer and forming a catalytic activation layer over a lop surface of the recessed second capacitor plate material, before selectively depositing a metallic diffusion barrier.

10. The method according to Claim 9, wherein forming the catalytic activation layer comprises depositing Pd.

11. The method according to Claim 1, further comprising depositing a third insulating layer over the at least one second capacitor plate, and forming a first conductive line making electrical connection to the second capacitor plate within the third insulating layer.

12. The method according to Claim 11 , further comprising forming via within die second insulating layer making electrical connection to the first capacitor plate, and forming a second conductive hne within the tiiird insulating layer making electrical connection to the via.

13. The method according to Claim 1, wherein forming at least one first capacitor plate comprises patterning the first insulating layer with a pattern for the first capacitor plate, and depositing an alloy-containing seed layer over the patterned first insulating layer, wherein selectively forming a first cap layer comprises passivating the top surface of the al least one first capacitor plalc by annealing the semiconductor wafer.

14. The method according to Claim 13, wherein a portion of the first cap layer is removed when patterning the second insulating layer, further comprising annealing the semiconductor wafer to repair die removed first cap layer, after patterning the second insulating layer.

15. The method according to Claim 1, wherein selectively forming a first cap layer comprises selectively depositing a metallic diffusion baiiier.

16. The method according to Claim 15, wherein depositing the metallic diffusion barrier comprises depositing CoWP, CoWB, CoP, NiMoP, Re or Ru.

17. The method according to Claim 15, further comprising:
recessing the first capacitor plate material below a top surface of the first insulating layer and forming a catalytic activation layer over a lop surface of the recessed first capacitor plate material, before selectively depositing a metallic diffusion barrier.

18. The method according to Claim 17, wherein forming the catalytic activation layer comprises depositing Pd.

19. The mediod according to Claim 1, wherein forming die second insulating layer comprises forming a second insulating layer comprising a thickness of 250 nm or less.

20. The method according to Claim 19, wherein forming the second insulating layer comprises depositing oxide, silicon dioxide, fluorinated silicate glass (FSG), a low dielectric constant material, or a porous low dielechic constant material.

21. The method according to Claim 1, wherein forming die second insulating layer comprises depositing a photosensitive low-k material.

22. The method according to Claim 21, wherein patterning the second insulating layer comprises utilizing UV iography or electron beam irradiation.

23. The method according to Claim 23 , wherein depositing the photosensitive low-k material comprises depositing as mefliylsilsesquiazane (MSZ).

24. The method according to Claim 1 , wherein forming at least one first capacitor plate comprises forming at least one first capacitor plate comprising copper, wherein depositing a second capacitor plate material comprises depositing copper.

25. Tlie method according to Claim 24, wherein forming at least one first capacitor plate comprises forming at least one first capacitor plate comprising Cu-Al, Cu-Mg, Cu-Sn, Cu-In, Cu-Zr, or Cu-Ag, wherein depositing a second capacitor plate material comprises depositing Cu-Al, Cu-Mg, Cu-Sn, Cu-In, Cu-Zr, or Cu-Ag.

26. A mctal-insulator-metal (MIM) capacitor, comprising:
a semiconductor wafer;
a first insulating material disposed over the wafer;
a firsl capacitor plate disposed over the semiconductor wafer within the firsl insulating material;
a first cap layer disposed over the first capacitor plate;
a second insulating layer disposed over the first insulating layer and first cap layer; a capacitor dielectric disposed over and abutting at least a portion of the first cap layer witiiin die second insulating layer;
a second capacitor plate disposed over and abutting the capacitor dielectric within the second insulating layer; and
a second cap layer disposed over the second capacitor plate.

27. The MIM capacitor according to Claim 26, wherein the first capacitor plalc and second capacitor plate comprise copper.

28. The MIM capacitor according to Claim 26, further comprising a dielectric cap layer disposed over the first insulating material.

29. Tlie MIM capacitor according to Claim 28, wherein the dielectric cap layer comprises SIN, SiC, SiCN or BloKI M, or a dielectric material with diffusion banner properties against metal ion or metal atom diffusion.

30. The MEVI capacitor according to Claim 26, wherein the first cap layer and second cap layer comprise a sclf-passivated layer formed by annealing.

31. The MEM capacitor according to Claim 26, wherein the first cap layer and second cap layer comprise selectively-deposited metallic diffusion banners.

32. The MIM capacitor according to Claim 31 , wherein the first cap layer and second cap layer comprise CoWP, CoWB, CoP, NiMoP, Re or Ru.

33. Tlie MIM capacitor according to Claim 26, further comprising:
a third insulating layer disposed over the second cap layer and the second insulating layer;
a first conductive line formed in the third insulating layer abutting the second cap layer; a via formed in the second insulating layer abutting the first cap layer; and a second conductive hne formed in the third insulating layer abutting the via.