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1. WO2003005782 - COUCHES D'EMPILEMENT AVEC SUBSTRATS SUPPORTANT DES DISPOSITIFS ELECTRONIQUES ET PROCEDE

Numéro de publication WO/2003/005782
Date de publication 16.01.2003
N° de la demande internationale PCT/US2002/021101
Date du dépôt international 02.07.2002
Demande présentée en vertu du Chapitre 2 31.01.2003
CIB
H01L 21/98 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
70Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun, ou de parties constitutives spécifiques de ceux-ci; Fabrication de dispositifs à circuit intégré ou de parties constitutives spécifiques de ceux-ci
98Assemblage de dispositifs consistant en composants à l'état solide formés dans ou sur un substrat commun; Assemblage de dispositifs à circuit intégré
H01L 25/10 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
25Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
03les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes H01L27/-H01L51/132
10les dispositifs ayant des conteneurs séparés
CPC
H01L 2224/04105
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
H01L 2224/18
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
18High density interconnect [HDI] connectors; Manufacturing methods related thereto
H01L 2224/24137
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
18High density interconnect [HDI] connectors; Manufacturing methods related thereto
23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
24of an individual high density interconnect connector
241Disposition
24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
24137the bodies being arranged next to each other, e.g. on a common substrate
H01L 2224/32245
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32245the item being metallic
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48225the item being non-metallic, e.g. insulating substrate with or without metallisation
48227connecting the wire to a bond pad of the item
Déposants
  • IRVINE SENSORS CORPORATION [US/US]; 3001 Redhill Avenue Suite 4-109 Costa Mesa, CA 92626-4573, US (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, IE, IT, JP, LU, MC, NL, PT, SE, SK, TR)
  • ANDREWS, Lawrence, D. [US/US]; US (UsOnly)
  • ALBERT, Douglas, M. [US/US]; US (UsOnly)
Inventeurs
  • ANDREWS, Lawrence, D.; US
  • ALBERT, Douglas, M.; US
Mandataires
  • DAWES, Daniel, L.; Myers, Dawes & Andras, LLP Suite 1150 19900 MacArthur Boulevard Irvine, CA 92612, US
Données relatives à la priorité
60/302,30602.07.2001US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) STACKABLE MICROCIRCUIT AND METHOD OF MAKING THE SAME
(FR) COUCHES D'EMPILEMENT AVEC SUBSTRATS SUPPORTANT DES DISPOSITIFS ELECTRONIQUES ET PROCEDE
Abrégé
(EN)
A Neo layer (107, 285) is provided with at least one die (10) having a microelectronic device on an active surface (55) of the die (10). The dies (10) are supported on a support substrate (105, 300) that can be readily handled by machines in an automated manufacturing setting. Both of the die (10) and the substrate (105, 300) are encapsulated in a layer material to provide a distinctive Neo layer or Neo PEM. The different embodiments offer additional respective advantages of improved manufacturability. Further versatility is provided by enabling use of dies (10) from different sources including bare dies (10) and dies (10) that are already packaged in a Plastic Embedded Microcircuit (PEM), for example. The ongoing goal of providing a stackable array of Neo layers (107, 285) is still met.
(FR)
La présente invention concerne une Néo couche (107, 285) avec au moins une puce (10) possédant un dispositif micro-électronique sur une surface (55) active de cette puce (10). Ces puces (10) sont supportées par un substrat (105, 300) support qui peut être manipulé sans délai par des machines dans un agencement de fabrication automatisé. Cette puce (10) et ce substrat (105, 300) sont encapsulés dans un matériau en couche de façon à donner une Néo couche ou un Néo PEM (microcircuit intégré plastique). Les différents modes de réalisation de l'invention offrent des avantages respectifs additionnels améliorant la fabrication. L'utilisation de puces (10) provenant de différentes sources comprenant des puces (10) nues et des puces (10) déjà jointes à des microcircuits intégrés plastique (PEM), par exemple, améliore encore la polyvalence de cette invention. L'objectif d'obtenir un réseau empilable de Néo couches (107, 285) est néanmoins atteint.
Dernières données bibliographiques dont dispose le Bureau international