Traitement en cours

Veuillez attendre...

Paramétrages

Paramétrages

1. WO2003005447 - STRUCTURE ET PROCEDE DE FABRICATION POUR MATRICES DRAM VERTICALES INTEGREES AVEC LIGNE BINAIRE A BASE DE SILICIURE ET INTERCONNEXIONS EN POLYSILICIUM

Numéro de publication WO/2003/005447
Date de publication 16.01.2003
N° de la demande internationale PCT/GB2002/002961
Date du dépôt international 27.06.2002
Demande présentée en vertu du Chapitre 2 09.08.2002
CIB
H01L 21/8242 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
70Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun, ou de parties constitutives spécifiques de ceux-ci; Fabrication de dispositifs à circuit intégré ou de parties constitutives spécifiques de ceux-ci
77Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun
78avec une division ultérieure du substrat en plusieurs dispositifs individuels
82pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
822le substrat étant un semi-conducteur, en utilisant une technologie au silicium
8232Technologie à effet de champ
8234Technologie MIS
8239Structures de mémoires
8242Structures de mémoires dynamiques à accès aléatoire (DRAM)
CPC
H01L 27/10864
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10844Multistep manufacturing methods
10847for structures comprising one transistor one-capacitor memory cells
1085with at least one step of making the capacitor or connections thereto
10861the capacitor being in a substrate trench
10864in combination with a vertical transistor
H01L 27/10876
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10844Multistep manufacturing methods
10847for structures comprising one transistor one-capacitor memory cells
10873with at least one step of making the transistor
10876the transistor having a trench structure in the substrate
H01L 27/10891
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10844Multistep manufacturing methods
10847for structures comprising one transistor one-capacitor memory cells
10882with at least one step of making a data line
10891with at least one step of making a word line
H01L 27/10894
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10844Multistep manufacturing methods
10894with simultaneous manufacture of periphery and memory cells
Déposants
  • INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, NY 10504, US
  • IBM UNITED KINGDOM LIMITED [GB/GB]; PO Box 41 North Harbour Portsmouth, Hampshire PO6 3AU, GB (MG)
  • INFINEON TECHNOLOGIES AG [DE/DE]; St. Martin Strasse 53 81669 Munchen, DE
Inventeurs
  • DIVAKARUNI, Ramachandra; US
  • GRUENING, Ulrike; DE
  • MANDELMAN, Jack; US
  • NESBIT, Larry; US
  • RADENS, Carl; US
Mandataires
  • MOSS, Robert, Douglas; IBM United Kingdom Limited Intellectual Property Law Hursley Park Winchester, Hampshire SO21 2JN, GB
Données relatives à la priorité
09/897,86802.07.2001US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) STRUCTURE AND METHOD OF FABRICATING EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT
(FR) STRUCTURE ET PROCEDE DE FABRICATION POUR MATRICES DRAM VERTICALES INTEGREES AVEC LIGNE BINAIRE A BASE DE SILICIURE ET INTERCONNEXIONS EN POLYSILICIUM
Abrégé
(EN)
A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
(FR)
Cette invention concerne une structure et un procédé de fabrication de cellules DRAM verticales intégrées consistant à fabriquer des cellules MOSFET DRAM verticales avec des couches de polysilicium dans les régions matricielles, le support et/ou les structures d'interconnexion, la source support et les régions de drain et/ou l'empilement de portes. Ce procédé rend superflu l'emploi d'une couche de métallisation M0.
Dernières données bibliographiques dont dispose le Bureau international