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1. WO2001078237 - MODIFICATION RAPIDE EN RAMPE DE LA TENSION DE COMMANDE, AVEC RESOLUTION AMELIOREE

Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

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CLAIMS
What is Claimed is:
1. A method of generating a control voltage from a logic circuit having a first digital to analog converter having L bit control and a second digital to analog converter having N bit control, wherein L is less than N, said method comprising the steps of:
generating a control voltage signal based on output from said first
digital to analog converter for a first time period; said output from said first digital to analog converter based on an input voltage
reference signal having a first state; and
changing the state of said input voltage reference signal from said
first state to a second state and generating said control voltage
signal based on output from said second digital to analog
converter; said output from said second digital to analog
converter based on said input voltage reference signal in said
second state.
2. The method of claim 1 further comprising the steps of:
routing said output from said first digital to analog converter to a filter having a capacitor to charge said capacitor;
routing said output from said second digital to analog converter to
said filter to charge said capacitor;
wherein said output from said first digital to analog converter
accelerates the charging of said capacitor with respect to the
output of said second digital to analog converter.

3. The method of claim 2 wherein said output from said first digital to analog converter accelerates the charging of said capacitor with respect to the output of said second digital to analog converter by a factor of 10.
4. The method of claim 2 further comprising, prior to said step of generating a control voltage signal based on output from said first digital to analog converter for a first time period, sleeping said first digital to analog converter and said second digital to analog converter and substantially discharging said capacitor.
5. The method of claim 1 wherein N equals ten and L equals eight.
6. The method of claim 1 wherein- said step of generating a control voltage signal based on output from said first digital to analog converter for a first time period
comprises routing said output from said first digital to analog
converter through a first circuit path having a first time constant;
said step of generating a control voltage signal based on output from said second digital to analog converter comprises routing said
output from said second digital to analog converter through a
second circuit path having a second time constant; and
said second time constant is larger than said first time constant.
7. The method of claim 6 wherein said second time constant is at least ten times larger than said first time constant.
8. A method of generating a control voltage from a logic circuit having a first digital to analog converter having L bit control and a second digital to analog converter having N bit control, wherein L is less than N, said method comprising: sleeping said first digital to analog converter and said second digital to analog converter;
thereafter, awakening said first digital to analog converter and supplying an input voltage reference signal having a first state and L control bits to said first digital to analog converter;
producing an output from said first digital to analog converter based on said first state of said voltage reference signal and said L control bits for a first time period;
awakening said second digital to analog converter;
after said first time period expires, changing the state of said input voltage reference signal to a second state; and
supplying said input voltage reference signal having said second state and N control bits to said second digital to analog converter and producing an output from said second digital to analog converter based on said second state of said voltage reference signal and said N control bits;
deriving a control voltage based at least on said output from said first digital to analog converter during said first time period and based on at least said output from said second digital to analog converter during a second time period after said first time period.

9 The method of claim 8 wherein said step of deriving a control voltage based at least on said output from said first digital to analog converter during said first time period and based on at least said output from said second digital to analog converter during a second time period after said first time period
comprises
routing said output from said first digital to analog converter to a filter having a capacitor to charge said capacitor,
routing said output from said second digital to analog converter to
said filter to charge said capacitor,
wherein said output from said first digital to analog converter
accelerates the charging of said capacitor with respect to the
output of said second digital to analog converter
10 The method of claim 9 wherein said wherein said output from said first digital to analog converter accelerates the charging of said capacitor with respect to the output of said second digital to analog converter by a factor of ten
11 The method of claim 8 wherein said first digital to analog converter is designed to supply a first amount of current during said first time period and wherein said second digital to analog converter is designed to supply a second amount of current during said second time period, and wherein said first amount of current is at least five times more than said second amount of current

12 The method of claim 8 wherein
said step of deriving said control voltage based at least on said
output from said first digital to analog converter during said first time period and based on at least said output from said second
digital to analog converter during a second time period after said first time period comprises routing said output from said first
digital to analog converter through a first circuit path having a first time constant during said first time period and routing said output from said second digital to analog converter through a second
circuit path having a second time constant after said first time
period, and
said second time constant is larger than said first time constant
13 The method of claim 12 wherein said second time constant is at least ten times larger than said first time constant
14 A method of generating a control voltage signal using the outputs of first and second digital to analog converters the output of said first digital to analog converter varying based on L control bits and a reference voltage supplied to said first digital to analog converter, said method comprising the steps of
generating a control voltage signal by selectively adjusting said
reference voltage to emulate greater than L-bit control of the
output of said first digital to analog converter for a predetermined time period, and thereafter, continuing to generate said control voltage signal based
on the output of said second digital to analog converter but not
said first digital to analog converter.
15. The method of claim 14 wherein the output of said second digital to analog converter varies based on N control bits, wherein L is less than N.
16. The method of claim 14 wherein said step of generating said control voltage by selectively adjusting said reference voltage to emulate greater than L-bit control of the output of said first digital to analog converter for a
predetermined time period comprises routing said output of said digital to analog converter to a filter including a capacitor to charge said capacitor.
17. The method of claim 16 wherein said step of continuing to generate said control voltage based on the output of said second digital to analog converter comprises continuing to generate said control voltage based on the output of said second digital to analog converter for a second time period, wherein said second time period is more than ten times said first time period.
18. The method of claim 17 wherein said first digital to analog converter is designed to supply a first amount of current during said first time period and wherein said second digital to analog converter is designed to supply a second amount of current during said second time period, and wherein said first amount of current is at least five times more than said second amount of current.
19. A control voltage generating circuit, comprising:
a first digital to analog converter with L bit control;

a second digital to analog converter with N bit control connected in parallel with said first digital to analog converter; wherein L is less than N;
a filter connected to said first digital to analog converter and said second digital to analog converter; said filter including a capacitor and having an output,
a voltage reference signal supplied to both said first digital to analog converter and said second digital to analog converter, said voltage reference signal having at least a first state and a second state;
said filter output varying sequentially between at least the following three modes:
i) a first mode wherein said filter output is based on said first digital to analog converter and said voltage
reference signal having said first state;
ii) a second mode wherein said filter output is based on
said second digital to analog converter and said
voltage reference signal having said second state;
iii) a sleep mode wherein said filter output is substantially zero.
said capacitor charging faster in said first mode than in said second mode.

20. The circuit of claim 19 further including a selectively enabled reference voltage adjustment circuit operative to change said voltage reference signal between said first state and said second state.
21 . The circuit of claim 20 wherein said reference voltage adjustment circuit includes an open drain transistor.
22. The circuit of claim 21 wherein said filter further comprises a first circuit path comprising said capacitor and a first resistor electrically disposed between said first digital to analog converter and said capacitor, and wherein said filter further comprises a second circuit path comprising said capacitor and a second resistor electrically disposed between said second digital to analog converter and said capacitor, said first circuit path having a first time constant associated therewith, said second circuit path having a second time constant associated therewith, wherein said second time constant is at least five times larger than said first time constant.