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1. WO1998058409 - PROCEDE DE MONTAGE DE PUCE DE SEMI-CONDUCTEUR, PROCEDE DE FABRICATION D'UNE STRUCTURE DE PUCE SUR PUCE ET PROCEDE DE FABRICATION D'UNE STRUCTURE DE PUCE SUR CARTE

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Numéro de publication WO/1998/058409
Date de publication 23.12.1998
N° de la demande internationale PCT/JP1998/002628
Date du dépôt international 15.06.1998
CIB
H01L 21/60 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
02Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
04les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
50Assemblage de dispositifs à semi-conducteurs en utilisant des procédés ou des appareils non couverts par l'un uniquement des groupes H01L21/06-H01L21/326185
60Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
CPC
H01L 2224/05624
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05617the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
05624Aluminium [Al] as principal constituent
H01L 2224/11
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
11Manufacturing methods
H01L 2224/1134
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
11Manufacturing methods
113by local deposition of the material of the bump connector
1133in solid form
1134Stud bumping, i.e. using a wire-bonding apparatus
H01L 2224/13
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
H01L 2224/13099
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
13099Material
H01L 2224/13144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
13099Material
131with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
13138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
13144Gold [Au] as principal constituent
Déposants
  • KABUSHIKI KAISHA TOKAI-RIKA-DENKI-SEISAKUSHO [JP]/[JP] (AllExceptUS)
  • TANIGUCHI, Masahiro [JP]/[JP] (UsOnly)
  • USUI, Shinji [JP]/[JP] (UsOnly)
  • HORIBE, Masaru [JP]/[JP] (UsOnly)
Inventeurs
  • TANIGUCHI, Masahiro
  • USUI, Shinji
  • HORIBE, Masaru
Données relatives à la priorité
9/15890016.06.1997JP
Langue de publication japonais (JA)
Langue de dépôt japonais (JA)
États désignés
Titre
(EN) PROCESS FOR MOUNTING SEMICONDUCTOR CHIP, PROCESS FOR MANUFACTURING CHIP-ON-CHIP STRUCTURE, AND PROCESS FOR MANUFACTURING CHIP-ON-BOARD STRUCTURE
(FR) PROCEDE DE MONTAGE DE PUCE DE SEMI-CONDUCTEUR, PROCEDE DE FABRICATION D'UNE STRUCTURE DE PUCE SUR PUCE ET PROCEDE DE FABRICATION D'UNE STRUCTURE DE PUCE SUR CARTE
front page image
Abrégé
(EN)
A process for mounting a semiconductor chip, comprising the bump forming step followed by the bonding step. The bump forming step comprises forming a group of first gold-containing bumps (4) on a semiconductor chip (2) through a wire bonding device (11) and, at the same time, forming a group of second gold-containing bumps (5) on an object (3) to be mounted with the chip (2), and uniting the semiconductor chip (2) and the object (3) in one body with a predetermined gap between the chip (2) and the object (3) by performing flip chip bonding in a state where the group of the first gold-bearing bumps (4) and the group of second gold-containing bumps (5) are faced to each other by utilizing the wire bonding device (11).
(FR)
L'invention concerne un procédé de montage d'une puce de semi-conducteur, le procédé comprenant une phase de formation de bosses suivie d'une phase de soudage. La phase de formation de bosses consiste à former un groupe de premières bosses (4) contenant de l'or sur une puce de semi-conducteur (2) au moyen d'un dispositif (11) de soudage des connexions et, en même temps, à former un groupe de deuxièmes bosses (5) contenant de l'or sur un objet (3) destiné à être monté avec la puce (2), puis à réunir la puce de semi-conducteur (2) et l'objet (3) en un corps unique, un espace prédéterminé étant défini entre la puce (2) et l'objet (3), par soudage de puces à bosses dans une disposition dans laquelle le groupe des premières bosses (4) contenant de l'or et le groupe des deuxièmes bosses (5) contenant de l'or se font face au moyen du dispositif (11) de soudage des connexions.
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