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1. (WO1980002491) DISPOSITIF D"ENTREE-MAINTIEN EN VIE POUR DISPOSITIF DE TRANSFERT DE CHARGE DE PLASMA
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INPUT-KEEP ALIVE ARRANGEMENT
FOR PLASMA CHARGE TRANSFER DEVICE

Technical Field
This invention relates to plasma charge trans-fer devices of the kind including an array of transfer electrodes separated by dielectric material from an ionizable medium, control means coupled to said transfer electrodes and adapted to control the transfer of discharges in said medium along said device from an input position to an output position in accordance with charges transferred along said dielectric material, and an electrode pair located at said input position, each electrode of said electrode pair being separated by dielectric material from said ionizable medium.
The invention also relates to a method of operating a plasma charge transfer device.

Background Art
A plasma (gas ionization) charge transfer device of the kind specified is known from U.S. Patent Specification No. 3,781,600 in the name of Coleman and Kessler. One method of fabricating such devices is explained in U.S. Patent No. 3,810,686, issued May 14, 1974, to Coleman. Both patents are assigned to NCR Corporation. Such devices are operable as memory regis-ters, as recirculating registers or as display devices, and either in a static or a dynamic mode. As described in the above Coleman and Kessler patent, U.S. 3,781,600, a linear charge transfer channel can be operated in parallel with similar channels to form alphanumeric characters and can be expanded to increase the number of characters in a line without increasing the address electronic cost.
The plasma charge transfer device described in the Coleman and Kessler patent is shown in Fig. 1 in the form of a four-phase shift register 10. The shift register 10 comprises enclosure-forming plates 12-12 of any suitable dielectric material. Such as clear
glass, which define a channel 13 containing an ionizable gas such as neon and nitrogen. A plurality of transfer electrodes 14-14 (which may be transparent) are located on inner walls 16-16 of the plates opposite one another in parallel, but laterally offset relationship to subject the ionizable gas to an electric field when a suitable potential is applied across any two
opposing electrodes.
Input electrode I and erase electrode E are located at opposite ends of the linear transfer electrode array. In the embodiment shown, all transfer
electrodes 14-14, but not the input electrode I or the erase electrode E, are coated with a dielectric layer
18. The ionizable gas between any two adjacent opposing electrodes, including input electrode I and the nearest opposite transfer electrode, or the erase
electrode E and the nearest opposite transfer electrode effectively forms a gas cell that is dischargeable when subject to a suitable potential.
Binary information is entered into the device 10 at the first cell, which is formed between the input electrode I and the nearest electrode 1. Whether the binary information entered at a particular clock time is a 1 or a 0 depends upon whether or not the voltage across the first cell exceeds the gas discharge or
firing voltage, Vf. The binary information is stepped along the device by the transfer electrodes 14-14 to a display position or to an output position at the opposite end of the device, then is shifted out of the device at the erase electrode E.
Operation of the device 10 is controlled by the pulsing and magnitude of the voltage, V., applied to the input electrode, the voltage V •__> applied to the transfer electrodes, and the voltage V applied to the erase electrode, and by the magnitude of the voltage V c

_ OMPI results from the charge Q deposited on the dielectric walls 19-19 by the firing or discharge of a
cell. These voltages are chosen so that:
Vi > Vf <D'

Vs < Vf (2),

Vi-Vs < Vf (3)'

s + Vwc > Vf (4).

As indicated by equations (1), (2) and (4),
input voltage V- is greater than the discharge voltage
V , and sustaining voltage V is less than Vf and will
not cause discharg 3e unless combined with V,,c . A com-bination of voltages, gas compositions, and gas pressures suitable for the operation of the shift register
10 is given here by way of example only. The voltages
are Vf - 180v, V. ~ 200v, and Vc ~ 160v. A typical
pulse width is 20 microsec. The ionizable gas is 100%
Ne. The gas pressure is about 300 millimeters of
mercury.
The device 10 is arranged to receive digital
information every fourth clock time, at t = 1, 5, 9,
etc. The transfer electrodes 14-14 are connected as
four sets —1, 2, 3, 4— each of which is normally
maintained at V , and is pulsed to Ov. every fourth
clock time. The electrode sets 1, 2, 3 and 4 are
pulsed to Ov. at t = 1, 5, 9, etc.; t = 2, 6, 10, etc.;
t = 3, 7, 11, etc.; t = 4, 8, 12, etc.; respectively,
and are maintained at V at other times. Thus, if the
input electrode I is pulsed to V. at any time other
than t = 1, 5, 9, etc., the voltage V on electrode 1
opposes V. and equation (3) applies to preclude the
first cell from discharging.
For convenience, each member of a group of
four adjacent transfer electrodes 1, 2, 3, 4 is identi- ξAA EA {
_OA.PI
y fied by a subscript which is the group number. The group numbers are arranged in ascending order from the input end to the erase end of the channel 16. The group nearest the input electrode is thus 1-,, 2-., 3-., 41,; the last group is ln, 2n, 3n, 4n« See Fig. 1.
To enter a digital "1" into the device 10 at time t = 1, 5, 9, etc., the input I is taken to V. so that, with the electrodes 1 at Ov., equation (1) applies to the first cell I- , and discharge occurs there. If a digital "0" is to be input, the input electrode I is allowed to remain at Ov. The digital

"1" discharge applies positive charge of voltage Vwc to the cell wall having the lower polarity. In this case, the lower polarity wall is associated with electrode 1,.
The wall charge shortly extinguishes the discharge. However, the timing of the 1234 sequence of transfer electrode pulsing is selected so that electrodes 2 are taken to Ov. and electrodes 1 back to V before the wall charge dissipates. Because of this Ov. potential on electrode 2_- and the Vg and V voltages on electrode 1,, equation (4) applies and the cell
formed by the electrodes l-j-2, discharges. Discharge again leaves positive wall charge on the lower polarity wall, here the wall of electrode 2-,. Again, the wall charge extinguishes the discharge and the associated voltage, V WC , is algebraically added to Vs to discharge the next adjacent cell, which is formed by the electrodes 2-, -3-1. This sequential transfer of discharge and wall charge continues as long as the sequential
1234 pulsing of the transfer electrodes prevails.
Consequently, the information entered at the first cell can be transferred to a desired position within the channel or to the erase electrode E for destruction.
Note that the sequential pulsing of the
transfer electrodes 14-14 occurs during the input of information as well as during transfer thereof. This permits previously entered information to be trans-

■ WiP ferred serially along the device simultaneously with the entering of additional information which may occur once every four clock times of the transfer electrodes.
If it is desired to stop the shifting of information and to retain the information in place at any time, the sequence of transfer pulses is changed to what Coleman and Kessler refer to as the "hold" mode. One such sequence involves alternately pulsing two adjacent sets of the electrodes, such as sets 3 and 4, while the other two sets are maintained at a constant voltage.
A 14321234 hold sequence is taught in U. S. Patent No. 4,051,409 issued September 27, 1977 to D. G. Craycraft and assigned to NCR Corporation. The Cray-craft hold sequence prevents charge build up on electrodes adjoining the display cells and thereby facilitates shifting charge information after the hold sequence without reloading.
After the load sequence, shifting is reinstated when desired by reverting to the 1234 sequence of transfer electrode pulsing.
Shifted information is erased as it reaches the erase electrode E by applying the voltage pulse sequence of the transfer electrodes 1 to the erase electrode. Upon discharge of the next to the last cell in the device (the cell formed by the electrodes 3 -4 adjacent the erase electrode E) , positive wall charge is formed on the wall of the electrode 4 . Then, upon discharge of the last cell, 4 -E, the positive wall charge is transferred to the direct-coupled erase electrode and "extinguished" by the ground potential on the erase electrode.
The device 10 may be utilized either as a shift register memory or as a display device. The hold mode gives the device memory. When used as a shift register memory, the input pulse, resulting discharge, and associated wall charge (or their absence) represent a bit of binary information which is transferred along the device by the above-described charge transfer mechanism. As mentioned, the presence of the input pulse represents digital "1" and the absence of an input pulse represents digital "0" (or vice versa) as information is clocked into the register and transferred out. The information is transferred along the length of the device 10 until it is coupled to the output location where it can be read optically or electrically. For example, when a bit of information reaches the last cell position, the discharge there can be read optically by a conventional photodetector which produces an output signal that is read by any suitable device. Alternatively, the discharge can be read by direct electronic sensing of the charge transferred from the last electrode position to the erase electrode.
Because light is a by-product of the gas discharge, the device 10 can be used as a display in which the input pulse is transferred serially as described above. The absence of an input pulse forms an unlighted or blank cell or dot on the display, whereas an input pulse results in a lighted cell or dot. The displayed information can be loaded into the device and then held in place to provide a stationary display, or may be shifted continuously across the device. As mentioned previously, the single channel device 10 can be operated in parallel with similar devices so that the cells or dots form readable alphanumeric characters.
The plasma charge transfer device 10 of Fig. 1 is exemplary of the present state of the art in its use of three electrodes for input and keep-alive func-tions. The single input electrode I may be directly coupled to the ionizable gas (Fig. 1) or covered with dielectric 18 and thereby capacitively coupled to the gas (Fig. 2) in the same manner as the transfer electrodes 1, 2, 3- and 4. In this latter case, an input voltage of greater magnitude is likely required.
The pair of electrodes KA^ and KA2 shown in Figs. 1 and 2 form a keep-alive cell. The keep-alive electrodes are capacitively coupled to the gas and connected to a source of alternating voltage of sufficient magnitude and frequency to repetitively discharge the gas within the keep-alive cell. This pro-vides a sufficient supply of ionized particles to insure discharge of the cell formed by input electrode I and the first transfer electrode 1- and thereby to insure the input of data into the shift register or display.
The above-described three-electrode keep alive-input arrangement is effective. There are disadvantages however. The three electrodes are somewhat cumbersome and require separate input and keep-alive circuitry. The life of the DC input electrodes can be shortened by sputtering effects. And, the large keep-alive electrodes necessitate* weaving the input electrodes around them for external connection.

Disclosure of the Invention
It is an object of the present invention to provide a plasma charge transfer device of the kind specified wherein the aforementioned disadvantages are alleviated.
Therefore, according to the present invention there is provided a plasma charge transfer device of the kind specified, characterized in that said control means is arranged to selectively apply input potentials between one of said electrode pair and a transfer electrode at said input position, thereby initiating a discharge in said medium to selectively provide said charge on the dielectric material adjacent said transfer electrode at said input position, and in that said control eans is further adapted to repetitively apply keep- alive potentials across said electrode pair to repetitively discharge said medium at said input position.
According to another aspect of the invention, there is provided a method of operating a plasma charge transfer device including an array of transfer electrodes covered by dielectric material and thereby isolated from an ionizable medium, including applying transfer potentials to said transfer electrodes to con-trol the transfer of discharges in said medium along said device from an input position to an output position, characterized by the step of selectively applying input potentials across a first cell having walls defined by the dielectric material covering a first one of an electrode pair located at said input position and an adjacent one of said transfer electrodes to discharge the medium within said first cell, and by the step of repetitively applying potentials across a second cell having walls defined by the dielectric material covering said electrode pair to ionize said medium thereby facilitating discharge within said first cell.

Brief Description of the Drawings
Fig. 1 is a schematic cross-sectional view of a prior art plasma charge transfer device;
Fig. 2 is a partial schematic cross-sectional view of the device of Fig. 1 showing a capacitive-coupled input;
Fig. 3 is a schematic cross-sectional view of a plasma charge transfer device embodying the princi-pies of the present invention;
Fig. 4 is a schematic representation of a control circuit employed with a multiplicity of devices embodying the present invention;
Fig. 5 is a timing diagram showing waveforms for operating the device of Fig. 3 in load, hold, shift and erase modes;

Figs. 6 and 7 are timing diagrams showing wave forms for operating the device of Fig. 3 in an alternative erase mode and an alternative load mode, respectively, which leave the erase cell and the input-keep alive cell charge neutral;
Figs. 8-10 are charts showing discharge and charge transfer in the device of Fig. 3 in relation to the electrodes and to time during operation according to Fig. 5;
Figs. 11 and 12 are charts showing discharge and charge transfer in the device of Fig. 3 in relation to the electrodes and to time during the alternative erase and load modes, respectively, according to Figs. 6 and 7 ;
Fig. 13 is a schematic representation of the erase cell of Fig. 3 at various times just before, during and after a charge-neutral erase sequence;
Fig. 14 illustrates the appearance of the character "3" when displayed by the apparatus of Fig. 4; and
Fig. 15 is a timing diagram showing waveforms for operating the device of Fig. 4 to form the character "3" of Fig. 9.

Best Mode for Carrying Out the Invention
Fig. 3 illustrates an exemplary plasma charge transfer device 30 embodying the principles of the present invention. The input-keep alive electrodes I, In are fixed on opposite, inner plate walls 16-16 at one end (the left or input end) of the channel. The erase function is performed by a pair of electrodes E, Efi located on opposite walls at the opposite end (the right or erase end) of the channel. Both the pair of input-keep alive electrodes and the pair of erase electrodes have a dielectric coating 18, i.e., are capacitively coupled to the ionizable gas, although the erase electrodes could be direct-coupled to the gas in the manner of Coleman and Kessler, U. S. 3,781,600.
The components of the device 30 other than the input- keep alive and erase electrodes are common to and
given the same numerical designation as the components - of the Coleman and Kessler device 10 (Fig. 1).
As discussed relative to the Coleman and
Kessler patent, all the electrodes 14-14 with the same number designation 1, 2, 3 or 4 are connected in common. Clock pulses are applied sequentially and repeti- tively to the l 2, 3, 4 electrode buses 31-34, respectively. Thus, a 0 volt pulse on the 1 bus 31 is applied to all electrodes 1; and a 0 volt pulse on bus
32, bus 33, or bus 34 is applied to all electrodes 2,
3 or 4. Accordingly, and as more fully described in the Coleman and Kessler patent, information is loaded into the device 30 by applying/not applying an input pulse in conjunction with a transfer electrode clock pulse. This permits shifting of several bits of infor- . mation simultaneously along the channel, and the input of information simultaneously with shifting.
The above description applies to a single
channel device 30 and results in one or more "dots" of light along the length of the channel as pulses are
applied. As used here, a "dot" of light or the lack thereof generally refers to a location within a single group of four transfer electrodes. Thus, each group of four transfer electrodes represents a single bit position. In order to display letters, numerals, etc., a plurality of channels 30 can be used together. Fig. 4 illustrates one such arrangement, a display panel 40 having n interconnected channels 30. The channels 30 are connected in parallel so that the cells of the
individual channels provide horizontal dimension to
alphanumeric or other characters, while the correspond- ing cells of the stacked array of channels provide
vertical dimension to the characters.
Referring further to Fig. 4, data lines 41-41 feed character generator 42 for operating input drivers 43 associated with the seven channels 30. The input drivers 43 in turn apply input voltage V- via lines 44 to the input-keep alive electrode I for each channel. Also, keep-alive drivers 46 are connected to corresponding lines 44 to apply keep-alive pulses to the input electrodes I and IQ in multiplexed operation with the input pulsing. Logic means 47 control the input drivers 43 and the keep-alive drivers 46, and also control transfer drivers 48 for pulsing the transfer electrode sets 1, 2, 3 and 4. In accordance with conventional practice mentioned above, all (or several of) the channels share the transfer drivers 48 so that transfer pulses are supplied simultaneously to each electrode 1 of every channel, each electrode 2 of every channel, etc. The control logic 47 also controls erase drivers 49 which apply erase pulses V , V to the erase electrodes E and E 0*
The arrangement of Fig..4 is very similar to the control circuitry disclosed in the aforementioned U. S. Patent No. 4,051,409 to Craycraft. However, there are two differences. First, the keep-alive drivers 46 and the input drivers 43 are interconnected to permit multiplexed operation of the input pulses and the keep-alive pulses. Also, the erase drivers 49 apply Ve and V pulses to the pair of erase electrodes and do so in synchronism with the transfer electrode clock pulses. Given the circuit arrangement of Fig. 4, the waveform diagram(s) of Fig. 5, or 6 and 7 and the charge transfer charts of Figs. 8-10 or 11 and 12, the present invention will be readily implemented by those skilled in the art.
Referring now to Fig. 5, there is shown a timing diagram for loading consecutive 1, 0 bits of information into the channel 30, then holding, shifting, and erasing the information. The coordinated pulse timing diagram of Fig. 5 and charge transfer charts of Figs. 8-10 are for channel 30 having three groups or sets of transfer electrodes g = 1,2,3. The number of groups is illustrative only, and chosen solely because of space limitations.
The exemplary clock time interval is 20 microseconds ( ys). Times for each mode of operation start at t = 1 in Fig. 5. Accordingly, the load 1, 0 and erase modes each have times t = 1, 2, ...8 which represent two consecutive clock time cycles. The illustrated shift mode occupies one clock time cycle. The clock sequence is changed during the hold mode as described below, but still involves four clock times per cycle. Two clock cycles are shown for the hold mode. The number of clock cycles shown is illustra-tive only.
The keep-alive function is implemented by twice reversing the polarity of the voltage applied across the input-keep alive cell at the third and fourth clock times of each clock time cycle. This dual polarity reversal occurs in Fig. 5 during loading at load times t = 3 and 4; 7 and 8. Input IQ is normally at V and is switched from V volts to 0 v. at t = 3 and t = 7, then is returned to V at t = 4 and t = 8.

Input I, which is normally at 0 volts, is switched to VVi^ vv.. aatt t=3 and t=7, then is returned to 0 v. at t=4 and t=8.
As shown in the pulse transfer charts of Fig.

8, each polarity reversal at load t=3, 7, etc. produces a discharge across the cell defined by I-IQ*- These discharges provide ionized particles to facilitate discharge between the input electrode I and the first transfer electrode for loading information onto the transfer electrodes.
Referring again to Fig. 5, keep-alive dis-charges are not needed during the hold, shift (unless loading is being done also) , and erase operations.
However, the keep-alive discharging may be continued during these modes without interference with the operation of the device.
Information loading is performed by selectively applying/not applying 15 us input pulses at load clock times t=l, 5, etc. between the keep-alive pulses in conjunction with the transfer electrode pulsing. From Fig. 5, the transfer electrode sets are taken to 0 volts, one transfer electrode set per clock time, in the sequence 1234. The illustrated two load clock cycles thus involve twice pulsing each transfer electrode to 0 v. All electrodes 1 are pulsed to 0 v. at load clock times t=l, 5, etc. Similarly, electrodes 2; 3; and 4 are pulsed to 0 v. at the respective load clock times 2, 6, etc.; 3, 7, etc.; and 4, 8, etc.
This transfer pulse sequence is also used for the shift and erase modes of operation.
Referring further to Fig. 5, assume that previous keep-alive pulsing has left sufficient wall charge on the wall 19 of electrode I to insure loading, as shown at load time t=0, Fig. 8. To load a 1 bit onto the shift register, at load clock time t=l input electrode I is switched to V. v. for about 15 microseconds in conjunction with the switching of electrodes 1 to 0 v. Equation (1) holds, the cell formed by I-1-, is fired, and positive and negative wall charges
(indicated by + and - ) resulting from the discharge are attracted to the dielectric walls 19 of the cell

1-1-,. The positive charge is attracted to the wall having the lower potential, here the wall of electrode 1*,*■ . The associated wall charge potential Vwc opposes the potential V. and quickly extinguishes the discharge, leaving the wall charge on the cell walls as shown at load time 1.
It is emphasized that the discharges shown at the various times in Fig. 8-10, (for example load time 1) are based upon the wall charge condition which existed at the preceding clock time, (in this case, load time 0), but the wall charge shown at each time is the wall charge which results from the discharge shown at the same time. Also, the ions associated with each discharge at least partially neutralize any residual charge on adjacent electrodes, so that subsequent discharges restore any disruption of charge neutrality resulting from a previous discharge. Finally, the + and - symbols are intended merely as approximations of the wall charge and its location.
Input I is switched back to 0 volts at load time 1' (after about 15 us), causing another keep-alive discharge, and reducing the charge on electrode 1.
At load time t=2, transfer electrodes 1 are returned to V and electrodes 2 are switched to 0 v. The wall charge associated with electrode 1, (see load time 1') adds to the potential V on the electrodes 1 in accordance with equation (4) to discharge the cell lτ-2-j. Again, the positive wall charge collects on the lower potential wall of the cell, (electrode 2,), extinguishing the discharge. This process of switching the transfer electrodes to 0 v. to discharge a cell and transfer wall charge occurs again at clock times t=3 and t=4 (Fig. 8B) . As a result, the positive charge is shifted to the wall of electrode 4,.
Note that the keep-alive pulses that occur at load times 3 and 4 refresh the wall charge on I-I in preparation for the next loading cycle, in addition to providing "priming" ions for the next loading cycle, but do not interfere with the transfer of information described above.
To load a 0 bit at load t=5, input electrode I is allowed to remain at 0 volts to preclude discharge between I and 1,, which is switched to 0 v. at load t=5 in accordance with the transfer electrode clock puls-ing. At load t=5, 6, 7, and 8 (Fig. 8B) , discharge and charge transfer occurs across cells
l2~22' -I'- l ' and 32- 2, respectively, in the manner described pre- viously to transfer the digital 1 to cell 3^-4- . In like manner, the 0 is transferred to cell 3-. -4-,. It should be noted that the 0 bit is characterized by a lack of discharge and a lack of wall charge transfer during its entry and "passage".
If desired, information bits 1 or 0 could be entered every subsequent fourth clock time. Alternatively, if the desired information form is the light from the discharge, a transparent plate or plates 12 (Fig* 3) can be used to display information in the form of lighted dots/unlighted dots.
The hold mode illustrated in Fig. 9 is accomplished by applying the Craycraft 14321234 sequence of Ov. pulses to the transfer electrodes. A single hold cycle thus utilizes eight clock times and five different electrodes. Referring to Fig. 9A and also to
Fig. 5, at hold t=l, transfer electrodes 1 and 4 are switched to Ov. and V v., respectively, and with positive wall charge on electrode 42 from the previous discharge at hold t=8, equation (4) holds and cell
^_~^-~ discharges. At hold t=2 , the transfer electrodes

1 are switched back to V_s and the electrodes 4 are taken to Ov. so that the wall charge on 1, causes the cell 42--I3 to fire in the reverse direction. The the rest of the hold sequence, 321234, to discharge the cells ^—3 r j-)-iη( -.η~i f 1Λ~2T, __.<■>—3o, o-*4η in sequence and thereby return the positive wall charge to 42 after the discharge at hold t=8. See also Fig. 9B. The hold sequence is useful, for example, to display information in the form of lighted messages at a
chosen location along the length of the channel 30.
This five electrode sequence and the four electrode sequence also taught in Craycraft are preferred hold sequences, for they facilitate subsequent shifting without reloading. A fuller description of the hold sequences is contained in the Craycraft patent.
The hold sequence is easily coordinated with the preceding and following sequences. As illustrated in Fig. 5, the preceding load sequence is completed by switching transfer electrodes 4 to Ov. at load time t=8 (or at the end of the last four-clock-time cycle of the load sequence) immediately preceding the first hold time. Also, the following shift or erase sequence is initiated by switching the transfer electrodes 1 to Ov. to commence the standard 1234 transfer electrode sequence.
A shift cycle is identical to the "load 0" cycle, i.e., the pulsing required is the 1234 transfer electrode pulse sequence illustrated in Fig. 5. This cycle is used to transfer information to a desired display location or to the end of the register in preparation for the erase operation. For example, after loading the 1 and 0 bits onto the first two bit positions of the three bit channel 30, and holding the information if desired, one shift cycle is necessary to transfer the digital information into position to initiate erasing. The charge associated with the 1 bit would be transferred to electrode 4-,; the 0 bit would be transferred to electrode 42.
The erase sequence involves coordinated pulsing of the E and EQ electrodes in synchronization with the normal transfer pulsing of the transfer electrodes. Alternative erase modes are shown in Figs. 10 and 11. The first mode, shown in Figs. 10A and 10B, sets the polarity of any residual wall charge on E-EQ to permit proper subsequent discharge and erase opera-tion. The same aim is accomplished during the second mode, shown in Figs. 11A and 11B, by eliminating residual charge on E-EQ.
First, consider use of the first erase mode for shifting out or erasing the "1" bit. At the last shift clock time (Fig. 5) electrode 43 was taken to

Ov. to discharge the cell 33~43 and apply the positive wall charge associated with the "1" bit to electrode 4-,.

This condition is represented in the first time-frame of Fig. 10A.
At the first erase clock time, electrode 43 is switched from Ov. to s v. , while E is at Ov.
Because of the positive wall charge remaining on electrode 43 from the last shift clock time, equation (4) applies and the cell 3-E discharges. This transfers the positive wall charge from 43 to E at erase t=l.
At erase t=2, electrode E is switched to V v., and EQ remains at 0 v. The cell E-EQ' is discharged, transferring positive wall charge to EQ.
Next, at erase t=3 , during pulses of about 10 microseconds duration (from t=3 to 3') E is switched to Ov. and EQ to Vs v. to fire the cell EQ-E in the re- verse direction. This restores the positive wall
- charge to electrode E.
Then, at erase time 3', the potential on electrode E is changed from O v. to V and stays at V —Z* for 30 μs until t=5 while EQ is also changed from V to 0 v. for 10 μs until t=4 , at which time it is again changed from 0 v. to V for 20 μs until t=5. This dis- charge at t=3 discharges the cell E-EQ in the original direction and leaves positive wall charge on EQ and negative wall charge on E. This last pulse concludes the first, four clock-time erase cycle, and places the charge on E and EQ in the proper polarity for the next erase cycle. See clock t=4 , Fig. 10B.
The four clock-time erase cycle is repeated to erase the "0" bit. This next cycle is shown at erase t = 5-8 of Figs. 5 and 10B. During the second erase cycle, the erase discharges occur at erase times 7 (clock t=3 ) and 7' (clock t=3.5). The second of these discharges places positive and negative wall charges on EQ and E, respectively, to prepare EQ and E for the next erase cycle.
Figs. 10A and 10B also illustrate the shifting into erase position of "0" and "1" bits which were entered into the channel subsequent to the "1" and "0" shown in Figs. 5 and 8.
It will be noted that the erase electrodes need not be pulsed during the other modes of operation.
Figs. 6 and 11A, B show the timing diagram and charge transfer charts, respectively, for the alternative, charge-neutral erase operation, erase mode II. Erase mode II differs from mode I, shown in Figs. 5 and 10, in that the V potential on electrode E is briefly dropped to Ov. at predetermined erase times

311, 7'', etc. In contrast, during mode I, E stays at Vs from 3' to 5, 7" to 9, 11' to 13, etc. With EQ at Ov. during mode I erase times 3'-4, 7'-8, ll'-12, etc., the discharge across E-EQ is of like duration and leaves the previously-described wall charges on E and Eg at erase t=4, 8, 12, etc. These charges permit proper functioning of the erase electrodes during subsequent erase cycles. Dropping the E potential to Ov. in mode II is done at the predetermined times 3'', 7'', 11", etc. at which the discharge has just brought the dielectric-covered walls of E-EQ to charge neutrality.
Thus, there is essentially no wall charge on E-EQ at mode II erase t=4, 8, 12, etc. and these electrodes are again ready for the next erase cycle. For the exe -plary plasma display channel 30, E can be dropped to Ov. at 3" (or 7", 11", etc.), i.e., time 3' + 5 microseconds. Note that depending on the gas mixture and gas pressure, the time for erasure can be less than one microsecond.
The positive and negative charge on EQ and E at mode I erase t=4 and 8 is shown in Fig. 10B, and the lack of charge which occurs when the discharge is cut short at mode II erase t=3 " , 7", and 11" is shown in Fig. 11B-D. Thus, of the three possible erase elec-trode charge situations — the charge on the erase electrodes (1) facilitating or (2) hindering erasing, or (3) the erase electrodes having essentially no charge, i.e., being charge-neutral — modes I and II provide the first and third, desirable situations.
The effect of the discharge-quenching pulse of erase mode II is shown schematically in Fig. 13. Fig. 13 is a representation of the discharge and charge state of the capacitive coupled EQ-E cell just before, during and after one erase sequence, illustratively from erase t=2+ to erase t=4. Just before and at erase t=3, there is positive and negative wall charge on E_ and E as the result of the discharge at erase t=2. At erase t=3, the potential across the cell is reversed. With V voltage on Eπ, the wall charge is additive to the applied voltage so that equation (4) applies and the cell is discharged. The discharge gradually rever-ses the polarity of the wall charge across the cell until, before t=3 ' , the reversed wall charge quenches the discharge. Then, at erase t=3 ' , the potential is again reversed. With V voltage on EQ, the wall charge is additive to the applied voltage so that equation (4) again applies and the cell is discharged in the reverse direction. Again the discharge commences reversing the wall charge. At t=3 ' ' , when there is no or very little wall charge on the cell, the potential is removed. This stops the discharge and the wall charge reversal, so that at erase t=4 , the charge-neutral erase cell E-EQ is ready for the next erase sequence. (In mode I, the potential applied across the erase cell continues until sufficient reversed-polarity wall charge is built up to quench the discharge. As stated previously, the polarity of this wall charge is such that normal load operation can continue. See Fig. 10B, t=4, 8.)
Referring now to Figs. 7 and 12, an alternative loading sequence, load mode II, is shown during the consecutive loading of 1,0,1. The wave forms, discharges, and resulting wall charges are identical to those shown in Figs. 5 and 8 for mode I, except for the use of the discharge-quenching polarity removal at load t=3", 7", 11", etc., which is identical to that described for the erase mode II operation.
Consider now the use of a seven channel, five bit display panel 40, Fig. 4, to load an alphanumeric character, arbitrarily chosen to be the numeral 3.
Fig. 15 illustrates the load (mode I) and transfer electrode pulses which are applied to the first five groups of a seven channel display panel 40 for forming the numeral 3, which is illustrated in Fig. 14. The control mechanisms continually operate the input drivers for the channels 1 through 7 so the input-keep alive electrodes are pulsed every four clock times to provide the keep-alive pulses, as described previously. As shown in Fig. 15, the same sequence of keep-alive pulses is applied to each input electrode IQ and I in every channel.
To initiate input of the numeral 3 , at the initial load clock time t=l the input drivers 43 for channels 1-7 increase the potential of the input electrodes I for the seven channels from Ov. to V-. v. The drivers 48 for the transfer electrodes 1 drive the potential for these electrodes from V to ground.
These "load 1" pulses are the relatively narrow 15 microsecond pulses illustrated at times t=l, 5, 9, 13, and 17 in Fig. 15. The potential difference applied across the input electrodes I and the transfer electrodes l-]_ provides discharge of all seven cells I-1-ι and places a positive charge on the dielectric wall of the first transfer electrode 1-, of each channel.
As shown in Fig. 10, the 2, 3, and 4 transfer electrode sets are then pulsed in sequence at load t=2, 3, 4 to move the charges on electrodes 1, to the electrodes 4-, of each channel.
Next, at load t=5, V^ input signals are again applied to channels 1, 4 and 7. This results in discharge and the development of new positive charges at the transfer electrodes 1-, of channels 1, 4 and 7. In addition, the potential difference developed between the transfer electrode 4, and the transfer electrode 12 shifts the initial positive charges to a position the transfer electrodes 12 of the seven channels. When the 2, 3, 4 transfer electrodes are then pulsed as illustrated, the positive charges are shifted to the transfer electrodes 4^ (channels 1, 4 and 7) and the transfer electrodes 42 (all channels).
At load time t=9, third V. input pulses are applied to the channels 1, 4 and 7 along with the 1234 transfer electrode pulsing. At load time t=13, fourth input pulses are applied to channels 1, 4, and 7, again with the 1234 pulsing. The final steps in producing the numeral 3 are initiated at load t=17 and involve V. pulsing of the input electrodes I for channels 1 and 7 and the 1234 transfer electrode pulsing. The result is the formation of the numeral 3 by the combination of the individual lighted cells, as shown in Fig. 14.
The position of the numeral 3 can be moved along the channels by continuing the 1234 transfer electrode pulsing. The numeral also can be held, can be shifted simultaneously with other information loading, and, ultimately, can be shifted to the erase electrodes and erased. All these modes are accomplished precisely as discussed previously. Of course, as long as additional input signals are not applied, only the numeral 3 will appear.
It should be emphasized that the times and time intervals given throughout are by way of example only, for those skilled in the art will readily adapt these and other parameters to their particular plasma apparatus and function to achieve optimum operation.