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1. JP2019179333 - INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND SEMICONDUCTOR DEVICE

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Office
Japon
Numéro de la demande 2018067216
Date de la demande 30.03.2018
Numéro de publication 2019179333
Date de publication 17.10.2019
Type de publication A
CIB
G06F 13/36
GPHYSIQUE
06CALCUL; COMPTAGE
FTRAITEMENT ÉLECTRIQUE DE DONNÉES NUMÉRIQUES
13Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
14Traitement de demandes d'interconnexion ou de transfert
36pour l'accès au bus ou au système à bus communs
G06F 13/38
GPHYSIQUE
06CALCUL; COMPTAGE
FTRAITEMENT ÉLECTRIQUE DE DONNÉES NUMÉRIQUES
13Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
38Transfert d'informations, p.ex. sur un bus
CPC
G06F 13/36
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
36for access to common bus or bus system
G06F 13/38
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
G06F 13/4282
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
4282on a serial bus, e.g. I2C bus, SPI bus
G06F 13/1668
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
G06F 13/404
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
4004Coupling between buses
4027using bus bridges
404with address mapping
G06F 12/1072
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
1072Decentralised address translation, e.g. in distributed shared memory systems
Déposants SOCIONEXT INC
株式会社ソシオネクスト
Inventeurs GOTO SEIJI
後藤　誠司
NIMODA EIICHI
仁茂田　永一
OKAMOTO SATOSHI
岡本　諭
YAMANE SHUICHI
山根　秀一
NISHIGUCHI YASUO
西口　泰夫
Mandataires 特許業務法人扶桑国際特許事務所
Titre
(EN) INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND SEMICONDUCTOR DEVICE
(JA) 情報処理システム、情報処理方法及び半導体装置
front page image
Abrégé
(EN)

PROBLEM TO BE SOLVED: To allow high speed memory access between master devices.

SOLUTION: Bridge devices 12 includes slave circuits 12a1 to 12a4 which are connected with each other via buses 12b and each of which is connected to one of master devices 11a1 to 11a4, functions as a slave to the connected master device, and performs communication according to a protocol in which the number of masters in a system is restricted. When the master device 11a1 makes access by specifying a first address of a memory 11b4 connected to the master device 11a4, the master devices 11a1 and 11a4 are allowed to communicate to the slave circuit 12a1 and the slave circuit 12a4 to which an address corresponding to the first address is specified via the bus 12b according to the addresses of the memories specified to respective slave circuits 12a1 to 12a4 and connected to the master devices to which respective slave circuits 12a1 to 12a4 are connected.

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2020,JPO&INPIT


(JA)

【課題】マスタ装置間での高速なメモリアクセスを可能とする。
【解決手段】ブリッジ装置１２は、バス１２ｂを介して相互に接続されるとともに各々がマスタ装置１１ａ１−１１ａ４の何れかに接続し、接続したマスタ装置に対するスレーブとして機能し、システム内でのマスタの数が制限されているプロトコルにしたがった通信を行うスレーブ回路１２ａ１−１２ａ４を備え、マスタ装置１１ａ１がマスタ装置１１ａ４に接続されたメモリ１１ｂ４の第１のアドレスを指定したアクセスを行うとき、スレーブ回路１２ａ１−１２ａ４の各々に対して設定された、スレーブ回路１２ａ１−１２ａ４の各々が接続するマスタ装置に接続されたメモリのアドレスに基づいて、スレーブ回路１２ａ１と、第１のアドレスに対応するアドレスが設定されたスレーブ回路１２ａ４と、バス１２ｂとを介して、マスタ装置１１ａ１，１１ａ４を通信させる。
【選択図】図１
Documents de brevet associés
WO/2019/188000
US20210011873
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