(EN) The invention provides a switch driver and a DAC system, each group of circuits is divided into two paths, each group of circuits comprises a first circuit, a second circuit and a third logic device, each of the first circuit and the second circuit comprises a first logic device and a second logic device connected with the first logic device, the clock signal frequency in each group of circuits is one half of the clock frequency; in each group of circuits, the phases of the input signals of the first circuit and the second circuit are different, the phases of the input signals of the first circuit in each group of circuits are the same, the phases of the input signals of the second circuit in each group of circuits are the same, and the first circuit and the second circuit are combined and output through a third logic device; the clock signal frequency of each group of circuits is reduced by half, and the data rate of each path in the switch driver is correspondingly reduced, so that the power consumption is reduced, the data period is doubled, the data acquisition is easier, and the time sequence requirement is correspondingly reduced.
(ZH) 本公开提供一种开关驱动器和DAC系统，将每组电路分成两路，各组电路分别包括第一电路、第二电路和第三逻辑器件，第一电路和第二电路分别包括第一逻辑器件和与该第一逻辑器件相连的第二逻辑器件，各组电路中的时钟信号频率为二分之一时钟频率；在每组电路中，第一电路和第二电路的输入信号的相位不同，各组电路中第一电路的输入信号的相位相同，各组电路中第二电路的输入信号的相位相同，第一电路和第二电路经第三逻辑器件合并输出；将各组电路的时钟信号频率降低一半，相应降低开关驱动器中每一路的数据率，从而降低功耗，数据周期增加一倍，数据采集更容易，对时序要求相应降低。
