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1. CN110780726 - Method and system for detecting rationality of power-on time sequence of PG pin, and related components

Office
Chine
Numéro de la demande 201910931266.0
Date de la demande 29.09.2019
Numéro de publication 110780726
Date de publication 11.02.2020
Numéro de délivrance 110780726
Date de délivrance 10.11.2020
Type de publication B
CIB
G06F 1/26
GPHYSIQUE
06CALCUL; COMPTAGE
FTRAITEMENT ÉLECTRIQUE DE DONNÉES NUMÉRIQUES
1Détails non couverts par les groupes G06F3/-G06F13/89
26Alimentation en énergie électrique, p.ex. régulation à cet effet
H03K 17/12
HÉLECTRICITÉ
03CIRCUITS ÉLECTRONIQUES FONDAMENTAUX
KTECHNIQUE DE L'IMPULSION
17Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts
12Modifications pour augmenter le courant commuté maximal admissible
H03K 17/22
HÉLECTRICITÉ
03CIRCUITS ÉLECTRONIQUES FONDAMENTAUX
KTECHNIQUE DE L'IMPULSION
17Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts
22Modifications pour assurer un état initial prédéterminé quand la tension d'alimentation a été appliquée
CPC
G06F 1/26
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
H03K 17/12
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
17Electronic switching or gating, i.e. not by contact-making and –breaking
12Modifications for increasing the maximum permissible switched current
H03K 17/22
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
17Electronic switching or gating, i.e. not by contact-making and –breaking
22Modifications for ensuring a predetermined initial state when the supply voltage has been applied
Déposants SUZHOU INSPUR INTELLIGENT TECHNOLOGY CO., LTD.
苏州浪潮智能科技有限公司
Inventeurs WANG JIAN
王健
Mandataires 北京集佳知识产权代理有限公司 11227
Titre
(EN) Method and system for detecting rationality of power-on time sequence of PG pin, and related components
(ZH) PG引脚上电时序合理性的检测方法、系统及相关组件
Abrégé
(EN)
The invention discloses a method for detecting rationality of a power-on time sequence of a PG pin. The method comprises the following steps: acquiring a pull-up level of the PG pin of a VR chip; determining the value of a pull-up resistor of the PG pin as a first resistance value when the current value of the pull-up level injected into the VR chip is equal to the maximum withstand current of theVR chip; acquiring equivalent resistance to ground when the PG pin is at a low level, and calculating a value of a pull-up resistor of the PG pin as a second resistance value based on the equivalentresistance to ground when the output voltage of the PG pin is equal to a preset interference voltage limit value; and when it is judged that the actual resistance value of the pull-up resistor is lower than the first resistance value or the second resistance value, outputting first prompt information. By means of the scheme, whether the power-on time sequence of the PG pin in the VR chip is reasonable or not can be determined, and misoperation of a subsequent circuit is avoided. The invention also provides a system for detecting the rationality of the power-on time sequence of the PG pin and arelated assembly. The system and the assembly have corresponding effects.

(ZH)
本发明公开了一种PG引脚上电时序合理性的检测方法,包括:获取VR芯片的PG引脚的上拉电平;确定出当上拉电平注入到VR芯片中的电流值等于VR芯片的最大耐受电流时,PG引脚的上拉电阻的取值,作为第一电阻值;获取PG引脚低电平时的对地等效电阻,并基于对地等效电阻计算出当PG引脚的输出电压等于预设的干扰电压限制值时,PG引脚的上拉电阻的取值,作为第二电阻值;当判断出上拉电阻的实际电阻值低于第一电阻值或者低于第二电阻值时,输出第一提示信息。应用本申请的方案,可以确定出VR芯片中的PG引脚上电时序是否合理,避免后续电路误动作。本申请还提供了PG引脚上电时序合理性的检测系统及相关组件,具有相应效果。

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