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1. CN109817531 - Array substrate and manufacturing method thereof

Office
Chine
Numéro de la demande 201910108116.X
Date de la demande 02.02.2019
Numéro de publication 109817531
Date de publication 28.05.2019
Numéro de délivrance 109817531
Date de délivrance 12.03.2021
Type de publication B
CIB
H01L 21/48
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
02Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
04les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
48Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes H01L21/06-H01L21/326218
H01L 23/498
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
23Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
48Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
488formées de structures soudées
498Connexions électriques sur des substrats isolants
CPC
G02F 1/136227
GPHYSICS
02OPTICS
FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01for the control of the intensity, phase, polarisation or colour 
13based on liquid crystals, e.g. single liquid crystal display cells
133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362Active matrix addressed cells
136227Through-hole connection of the pixel electrode to the active element through an insulation layer
H01L 21/76804
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76804by forming tapered via holes
H01L 27/124
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
124with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
H01L 27/1248
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
1248with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
H01L 21/48
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
H01L 23/498
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
Déposants HEFEI XINSHENG OPTOELECTRONIC TECHNOLOGY CO., LTD.
合肥鑫晟光电科技有限公司
BOE TECHNOLOGY GROUP CO., LTD.
京东方科技集团股份有限公司
Inventeurs CHENG LEILEI
程磊磊
FANG JINGANG
方金钢
DING LUKE
丁录科
LIU JUN
刘军
LI WEI
李伟
ZHOU BIN
周斌
Mandataires 北京润泽恒知识产权代理有限公司 11319
Titre
(EN) Array substrate and manufacturing method thereof
(ZH) 一种阵列基板及其制作方法
Abrégé
(EN)
The invention provides an array substrate and a manufacturing method thereof, and relates to the technical field of display. The manufacturing method comprises the steps of sequentially forming a first metal layer and an insulating layer on a substrate; forming an etching barrier layer on the insulating layer; etching the etching barrier layer and the insulating layer for multiple times to form aconnecting hole penetrating through the insulating layer, wherein the connecting hole comprises a plurality of through holes sequentially communicating with one another, and the slope angle of each through hole is smaller than a preset slope angle; and forming a second metal layer, wherein the second metal layer is connected with the first metal layer through the connecting hole. The etching barrier layer and the insulating layer are etched for multiple times, so that the formed connecting hole comprises a plurality of through holes sequentially communicating with one another; and the thickness of the insulating layer etched each time is small, so that the slope angle of each through hole in the formed connecting hole is smaller than the preset slope angle, poor coverage or broken line ofthe second metal layer caused by the large slope angle of the connecting hole is avoided during subsequent manufacturing of the second metal layer, and poor lap joint of the first metal layer and thesecond metal layer is improved.

(ZH)
本发明提供了一种阵列基板及其制作方法,涉及显示技术领域。本发明通过在衬底上依次形成第一金属层和绝缘层,在绝缘层上形成刻蚀阻挡层,对刻蚀阻挡层和绝缘层进行多次刻蚀,形成贯穿绝缘层的连接孔,连接孔包括多个依次连通的过孔,且每个过孔的坡度角均小于预设坡度角,形成第二金属层,第二金属层通过连接孔与第一金属层连接。通过对刻蚀阻挡层和绝缘层分多次进行刻蚀,使得形成的连接孔包括多个依次连通的过孔,且由于每次刻蚀掉的绝缘层厚度较小,保证形成的连接孔中的每个过孔的坡度角均小于预设坡度角,在后续制作第二金属层时,避免因连接孔坡度角较大导致第二金属层的覆盖不佳或断线,改善第一金属层与第二金属层的搭接不良。

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