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1. WO1987003435 - CMOS TO ECL INTERFACE CIRCUIT

Nota: Texto obtenido mediante procedimiento automático de reconocimiento óptico de caracteres.
Solo tiene valor jurídico la versión en formato PDF

CLAIMS

1. A CMOS to ECL interface circuit,
including input means (10) adapted to receive CMOS logic level signals and output means (60, 62) adapted to provide ECL logic level signals, characterized by first and second field effect transistors (22, 23; 35, 36; 45, 46) having respective first and second source-drain paths connected in series between a supply voltage source and a reference potential source, in that said second field effect transistor (23, 36, 46) is connected to operate in a body effect mode, and in that the junction point between said first and second source-drain paths is coupled to said output means, the arrangement being such that, in response to a first CMOS logic level input signal applied to said input means (10), said first field effect transistor (22, 35, 45) is operative to cause said output means (60, 62) to provide a first ECL logic level output signal, and in response to a second CMOS logic level input signal applied to said input means (10), said second field effect transistor (23, 36, 46) is
rendered operative in said body effect mode to cause said output means (60, 61) to provide a second ECL logic level output signal.

2. A CMOS to ECL interface circuit
according to claim 1, characterized in that said input means (10) is coupled to the gate electrodes of third and fourth field effect transistors (21, 24), having third and fourth source-drain paths connected in series with said first and second source-drain paths between said supply voltage source and said reference potential source.

3. A CMOS to ECL interface circuit
according to claim 2, characterized in that said first, second and third field effect transistors (22, 23, 21) are of a first conductivity type and said fourth field effect transistor (24) is of a second conductivity type, in that said first field effect transistor has its drain and gate electrodes connected to said junction point and its source electrode connected to the drain electrode of said third field effect transistor (21), in that said second field effect transistor (23) has its source electrode connected to said junction point and its drain and gate electrodes connected to the drain electrode of said fourth field effect transistor (24), in that said third field effect transistor (21) has its source electrode connected to said reference potential source and its gate electrode connected to said input means (10), in that said fourth field effect transistor (24) has its source electrode connected to said supply voltage source and its gate electrode connected to said input means (10), and in that said output means includes a resistor (62) coupled between said junction point a further supply voltage source.

4. A CMOS to ECL interface circuit
according to claim 1, characterized by fifth and sixth field effect transistors (34, 31; 44, 41) having respective fifth and sixth source-drain paths
connected in series between said junction point and said reference potential source, in that the gate electrode of said first transistor (35; 45) is
connected to a further junction point, location between said fifth and sixth source-drain paths, and in that said input means (10), is connected to the gate electrodes of said second, fifth and sixth transistors (36, 34, 31; 46, 44, 41).

5. A CMOS to ECL interface circuit
according to claim 4, characterized in that said input means (10) is coupled directly to the gate electrodes of said second and sixth transistors (36, 31) and, via inversion means (32, 33), to the gate electrode of said fifth transistor (34).

6. A CMOS to ECL interface circuit
according to claim 4, characterized in that said input means (10) is coupled directly to the gate electrode of said fifth transistor (44), and, via inversion means (42, 43), to the gate electrodes of said second and sixth transistors (46, 41).