正在处理

请稍候...

设置

设置

1. US20170097884 - Pipelined convolutional operations for processing clusters

专利局 美国
申请号 14874784
申请日 05.10.2015
公布号 20170097884
公布日 06.04.2017
授权号
授权日 06.02.2018
公布类型 B2
国际专利分类
G PHYSICS
06
计算;推算;计数
F
电数字数据处理
12
在存储器系统或体系结构内的存取、寻址或分配(信息存储本身入G11)
G PHYSICS
06
计算;推算;计数
F
电数字数据处理
12
在存储器系统或体系结构内的存取、寻址或分配(信息存储本身入G11)
02
寻址或地址分配;地址的重新分配
G PHYSICS
06
计算;推算;计数
F
电数字数据处理
15
通用数字计算机;通用数据处理设备
76
存储程序计算机的通用结构
G PHYSICS
06
计算;推算;计数
T
一般的图像数据处理或产生
1
通用图像数据处理
20
处理器结构;处理器配置,例如流水线
G06F 12/00
G06F 12/02
G06F 15/76
G06T 1/20
CPC
G06F 12/023
G06F 15/76
G06F 2212/251
G06T 1/20
申请人 Intel Corporation
发明人 Tony Werner
Aravind Kalaiah
Andrew Yang
Carey Kloss
Horace Lau
Naveen Gandham Rao
Amir Khosrowshahi
代理人 Alliance IP, LLC
标题
(EN) Pipelined convolutional operations for processing clusters
摘要
(EN)

Described herein are one or more integrated circuits (ICs) comprising controller circuitry to receive a command to execute an operation for data inputs stored in an external memory or a local memory, and convert the operation into a set of matrix operations to operate on sub-portions of the data inputs. The IC(s) further comprise at least one processing circuitry to execute the set of matrix operations, the processing circuitry to include ALUs, a local memory external to the ALUs and accessible by the ALUs, and processing control circuitry to create at least one matrix operand in the local memory (from the data inputs of the operation) comprising at least one of a scalar, a vector, or a 2D matrix, and provide memory handles corresponding to each of the matrix operands to one of the ALUs to access the respective matrix operands when executing a matrix operation.