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1. (US20070079070) Cache controller

专利局 : 美国
申请号: 11239481 申请日: 30.09.2005
公布号: 20070079070 公布日: 05.04.2007
公布类型: A1
国际专利分类:
G06F 12/00
G PHYSICS
06
计算;推算;计数
F
电数字数据处理
12
在存储器系统或体系结构内的存取、寻址或分配(信息存储本身入G11)
申请人: ARM Limited
发明人: Piry Frederic Claude Marie
Raphalen Philippe Jean-Pierre
Grisenthwaite Richard Roy
代理人: NIXON &; VANDERHYE, PC
优先权数据: 29239481 30.09.2005 US
标题: (EN) Cache controller
摘要: front page image
(EN)

A cache controller and a method is provided. The cache controller comprises: request reception logic operable to receive a write request from a data processing apparatus to write a data item to memory; and cache access logic operable to determine whether a caching policy associated with the write request is write allocate, whether the write request would cause a cache miss to occur, whether the write request is one of a number of write requests which together would cause greater than a predetermined number of sequential data items to be allocated in the cache and, if so, the cache access logic is further operable to override the caching policy associated with the write request to non-write allocate. In this way, in the event that the number of consecutive data items to be allocated within the cache exceeds the predefined number then the cache access logic will consider that it is highly likely that the write requests are associated with a block transfer operation and, accordingly, will override the write allocate caching policy. Accordingly, the write request will proceed but without the write allocate caching policy being applied. Hence, the pollution of the cache with these sequential data items is reduced.