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1. (WO2019066928) POWER MONITORING FOR A PROCESSING PLATFORM
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CLAIMS

1. Power monitoring circuitry to monitor a system power profile of processing tasks executing on a processing platform, the power monitoring circuitry comprising: an input to receive from the processing platform, a processing system signal indicating a power being consumed by the processing platform;

a counter to store a count value corresponding to an accumulated number of times that a warning threshold condition associated with a warning threshold value is satisfied by the received processing system signal in a count-accumulation time interval; and

wherein the count value is supplied to a power control circuit of the processing platform via a bus in response to a read request from the power control circuit, the power control circuit being responsive to the count value to control a performance level of the processing platform.

2. Power monitoring circuitry as claimed in claim 1, comprising a critical level comparator to compare the processing system signal with a critical threshold value and to determine if a critical threshold condition is triggered; and

throttle signal output circuitry to assert a throttle signal to the processing platform to activate a power-reducing feature of one or more components of the processing platform when the critical comparator indicates that the critical threshold condition is triggered.

3. Power monitoring circuitry as claimed in claim 1, comprising at least one further warning comparator to perform a respective further comparison and at least one further counter to store a respective further count value and wherein the at least one further count value is supplied to a power control circuit of the processing platform via a bus in response to a read request from the power control circuit, the power control circuit being responsive to the at least one further count value to control a performance level of the processing platform.

4. Power monitoring circuitry as claimed in any one of claim 1, wherein the processing system signal is one of a power signal, a voltage signal and a current signal.

5. Power monitoring circuitry as claimed in claim 4, comprising mode setting circuitry to set the power monitoring circuitry to operate in a first monitoring mode in which the warning threshold condition corresponds to at least one of the system power signal or system current signal being at or above the warning threshold value or to operate in a second monitoring mode in which the warning threshold condition corresponds to the system voltage signal being at or below the warning threshold value.

6. Power monitoring circuitry as claimed in claim 1 , wherein the count value is read by the power control circuit of the processing platform at a reading rate having a first time interval between successive read events and wherein the counter has a count resolution corresponding to a second time, wherein the first time interval is greater than the second time.

7. Power monitoring circuitry as claimed in claim 6, wherein when the count value is determined to be approaching saturation, the power control circuitry is arranged to at least one of: increase the reading rate or adjust the warning threshold value to reduce a likelihood of saturation occurring.

8. Power monitoring circuitry as claimed in claim 2, wherein the power control circuit is responsive to the count value to associate a low count value with a less-bursty workload having a given average power and to associate a high count value with a more bursty workload having the given average power and to increase an operating frequency of at least one processor of the processing platform when the workload is determined to be less bursty.

9. Power monitoring circuitry as claimed in claim 8, wherein the increase in the operating frequency for the less bursty workloads is controlled by the power control circuit depending on a rate of assertion of the throttle signal.

10. Power monitoring circuitry as claimed in claim 19, comprising a count encoder to perform a conversion of the count value obtained from the warning counter, the count value having a first number of bits, to an encoded count value having a second number of bits less than the first number of bits, the encoded count value depending upon a position of a most significant bit of the count value.

1 1. Power monitoring circuitry as claimed in claim 10, wherein the counter encoder comprises a first bit field to represent a mantissa and a second bit field to represent an exponent corresponding to the first warning count value.

12. Power monitoring circuitry as claimed in claim 11 , wherein the mantissa of the encoded first warning count value comprises a number of contiguous bits of the count value starting from the most significant bit and including a number of bits equal to a width of the first bit field.

13. Power monitoring circuitry as claimed in claim 2, comprising a debouncer to control a debounce time corresponding to a minimum duration for which the processing system signal is to sustain traversal of the critical threshold value to trigger output of the throttle signal.

14. Power monitoring circuitry according to claim 13, comprising a debounce time decoder to receive from a storage element an encoded value for the debounce time, the encoded value having a first number of bits and to decode the encoded value to supply to the debouncer a debounce time having a second number of bits greater than the first number of bits.

15. A voltage regulator for a processor comprising the power monitoring circuitry of any one of claims 1 to 14.

16. A battery charger comprising the power monitoring circuitry of any one of claims 1 to 14.

17. A power supply for a server or for a desktop computer comprising the power monitoring circuitry of any one of claims 1 to 14.

18. An apparatus comprising:

at least one processor;

power control circuitry to control a performance level of the at least one processor; and

the power monitoring circuitry of any one of claims 1 to 14.

19. The apparatus of claim 18 comprising one of: a mobile phone, a desktop computer and a mobile computer.

20. Power control circuitry for a processing platform, comprising:

an input to receive from the processing platform at least one count value, the count value corresponding to an accumulated number of times that a warning threshold condition associated with a warning threshold value is satisfied by a processing system signal of the processing platform in a count-accumulation time interval; and

power level adjustment circuitry for the processing platform to adjust a performance level of at least one component controlled by the processing platform based on the count value.

21. Power control circuitry as claimed in claim 20 comprising:

an input to receive from the processing platform, a critical warning signal indicating that a critical threshold condition has been triggered, the triggering indicating that a load power of the processing platform exceeds a power delivery limit of a power source; and power level adjustment circuitry for the processing platform to reduce a power consumption of the processing platform responsive to receipt of the critical warning signal.

22. Power level control circuitry as claimed in claim 21, wherein the power level adjustment circuitry is to adjust a power level utilization level of the processing platform based on the count value and the critical warning signal to maintain a stable system input power.

23. Machine readable instructions provided on at least one machine-readable medium, the machine-readable instructions, when executed, to cause processing hardware to:

receive from a processing platform, a processing system signal indicating a power being consumed by the processing platform;

store a count value corresponding to an accumulated number of times that a warning threshold condition associated with a warning threshold value is satisfied by the received processing system signal in a count-accumulation time interval; and

output the count value to a power control circuit of the processing platform via a bus in response to a read request from the power control circuit, the power control circuit being responsive to the count value to control a performance level of the processing platform.

24. Machine readable instructions as claimed in claim 23, comprising machine-readable instructions, when executed, to cause processing hardware to:

receive a critical warning signal indicating that a critical threshold condition has been triggered corresponding to a load power of a processing platform exceeding a power delivery limit of a power source; and

reduce a power consumption of the processing platform responsive to receipt of the critical power warning signal.

25. Machine readable instructions as claimed in claim 23 or claim 24, comprising machine-readable instructions, when executed, to cause processing hardware to:

adjust a power level utilization level of at least one component of the processing platform based on at least one of the threshold count and the critical power warning signal to maintain a stable system input power drawn from a power supply below the critical threshold regardless of a processing workload of the processing platform being constant-duty or bursty in nature.