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1. (WO2019066912) SELF-ALIGNED CONTACTS FOR THIN FILM TRANSISTORS
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Claims

What is claimed is:

1. A semiconductor device, comprising:

a substrate;

a U-shaped channel above the substrate, wherein the U-shaped channel includes a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area, the first channel wall intersects with the channel bottom at a first end and intersects with the source area at a second end, and the second channel wall intersects with the channel bottom at a first end and intersects with the drain area at a second end;

a gate dielectric layer above the substrate and in contact with the channel bottom;

a gate electrode above the substrate and in contact with the gate dielectric layer; and a source electrode coupled to the source area, and a drain electrode coupled to the drain area.

2. The semiconductor device of claim 1, further comprising:

a first spacer next to the first channel wall, the source area, and the source electrode; and a second spacer next to the second channel wall, the drain area, and the drain electrode.

3. The semiconductor device of any one of claims 1 -2, wherein the gate electrode is a bottom gate electrode between the substrate and the channel bottom, the gate dielectric layer is between the gate electrode and the channel bottom, and the semiconductor device further includes a passivation layer between the first channel wall and the second channel wall.

4. The semiconductor device of any one of claims 1 -2, wherein the gate electrode is a top gate electrode above the channel bottom, and between the first channel wall and the second channel wall, and the gate dielectric layer is above the channel bottom, separating the first channel wall and the second channel from the gate electrode.

5. The semiconductor device of any one of claims 1 -2, wherein the gate electrode is a first gate electrode, and the semiconductor device further includes a second gate electrode, the first gate electrode is between the substrate and the channel bottom, and the second gate electrode is above the channel bottom, between the first channel wall and the second channel wall.

6. The semiconductor device of any one of claims 1 -2, wherein the gate dielectric layer

includes silicon and oxygen, silicon and nitrogen, yttrium and oxygen, silicon, oxygen, and nitrogen, aluminum and oxygen, hafnium and oxygen, tantalum and oxygen, or titanium and oxygen.

7. The semiconductor device of any one of claims 1-2, wherein the U-shaped channel includes amorphous silicon, zinc oxide, amorphous germanium, polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silicene, S12BN, stanene, phosphorene, molybdenite, poly- III-V like InAs, InGaAs, InP, amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC).

8. The semiconductor device of any one of claims 1-2, wherein the gate electrode includes titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), or an alloy of Ti, Mo, Au, Pt, Al Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.

9. The semiconductor device of any one of claims 1-2, wherein the substrate includes a silicon substrate, a glass substrate, a metal substrate, or a plastic substrate.

10. The semiconductor device of any one of claims 1-2, wherein the semiconductor device is above an interconnect, and the interconnect is above the substrate.

11. A method for forming a semiconductor device, the method comprising:

forming a U-shaped channel above a substrate, wherein the U-shaped channel includes a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area, the first channel wall intersects with the channel bottom at a first end and intersects with the source area at a second end, and the second channel wall intersects with the channel bottom at a first end and intersects with the drain area at a second end;

forming a spacer conformally covering the first channel wall, the second channel wall, and the channel bottom;

forming a dummy oxide within a void next to the spacer;

removing a part of the source area and a part of the drain area aligned with the dummy

oxide and the spacer; and

forming a source electrode next to the source area, and a drain electrode next to the drain area.

12. The method of claim 11 , further comprising:

removing the dummy oxide;

removing a part of the spacer next to the channel bottom to expose the channel bottom and to form a first spacer and a second spacer.

13. The method of claim 12, further comprising:

forming a passivation layer between the first spacer, the second spacer, and in contact with the channel bottom.

14. The method of claim 12, further comprising:

forming a gate dielectric layer conformally covering the channel bottom, the first spacer, and the second spacer; and

forming a gate electrode within a void formed by the gate dielectric layer.

15. The method of any one of claims 1 1-14, further comprising:

forming a gate electrode above the substrate, before forming the U-shaped channel; and forming a gate dielectric layer above the gate electrode before forming the U-shaped channel.

16. The method of claim 15, wherein the gate dielectric layer includes silicon and oxygen, silicon and nitrogen, yttrium and oxygen, silicon, oxygen, and nitrogen, aluminum and oxygen, hafnium and oxygen, tantalum and oxygen, or titanium and oxygen.

17. The method of any one of claims 11 -14, wherein the U-shaped channel includes amorphous silicon, zinc oxide, amorphous germanium, polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silicene, S12BN, stanene, phosphorene, molybdenite, poly- III-V like InAs, InGaAs, InP, amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC).

18. The method of any one of claims 11-14, wherein the source electrode or the drain electrode includes titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), or an alloy of Ti, Mo, Au, Pt, Al Ni, Cu, Cr, TiAIN, HfAIN, or InAlO.

19. The method of any one of claims 11-14, wherein the substrate includes a silicon substrate, a glass substrate, a metal substrate, or a plastic substrate.

20. A computing device comprising:

a processor;

a memory device coupled to the processor, wherein the processor or the memory device includes a transistor, and the transistor includes:

a U-shaped channel above a substrate, wherein the U-shaped channel includes a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area, the first channel wall intersects with the channel bottom at a first end and intersects with the source area at a second end, and the second channel wall intersects with the channel bottom at a first end and intersects with the drain area at a second end;

a gate dielectric layer in contact with the channel bottom;

a gate electrode in contact with the gate dielectric layer; and

a source electrode coupled to the source area, and a drain electrode coupled to the drain area.

21. The computing device of claim 20, further comprising:

a first spacer next to the first channel wall, the source area, and the source electrode; and a second spacer next to the second channel wall, the drain area, and the drain electrode.

22. The computing device of any one of claims 20-21, wherein the gate electrode is a bottom gate electrode between the substrate and the channel bottom, the gate dielectric layer is between the gate electrode and the channel bottom, and the semiconductor device further includes a passivation layer between the first channel wall and the second channel wall.

23. The computing device of any one of claims 20-21, wherein the gate electrode is a top gate electrode above the channel bottom, and between the first channel wall and the second channel wall, and the gate dielectric layer is above the channel bottom, separating the first channel wall and the second channel from the gate electrode.

24 The computing device of any one of claims 20-21 , wherein the gate electrode is a first gate electrode, and the semiconductor device further includes a second gate electrode, the first gate electrode is between the substrate and the channel bottom, and the second gate electrode is above the channel bottom, between the first channel wall and the second channel wall.

25. The computing device of any one of claims 20-21, wherein the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board.