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1. (WO2019063203) TRANSACTION NESTING DEPTH TESTING INSTRUCTION
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CLAIMS

1 . An apparatus comprising:

an instruction decoder to decode instructions; and

processing circuitry to perform data processing in response to the instructions decoded by the instruction decoder, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction within a thread of data processing by the processing circuitry, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing circuitry is configured to prevent commitment of results of the speculatively executed instructions of the transaction until the transaction end instruction is reached, and to abort processing of the transaction when an abort event occurs before reaching the transaction end instruction;

wherein in response to decoding of a transaction nesting depth testing instruction by the instruction decoder, the processing circuitry is configured to set at least one status value to one of a plurality of states selected dependent on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth equals a predetermined number greater than zero, and at least one further state selected when the transaction nesting depth is greater than or less than the predetermined number; and

the instruction decoder is configured to support an instruction set architecture comprising at least one type of conditional branch instruction enabling the instruction decoder, in response to a single transaction nesting depth testing instruction followed by a single conditional branch instruction, to control the processing circuitry to set the at least one status value dependent on the transaction nesting depth and perform a conditional branch conditional on the at least one status value being in the first state.

2. The apparatus according to claim 1 , wherein said predetermined number is 1.

3. The apparatus according to any of claims 1 and 2, wherein said at least one further state comprises:

a second state selected when said transaction nesting depth is less than said predetermined number; and

a third state selected when said transaction nesting depth is greater than said predetermined number.

4. The apparatus according to claim 3, wherein the instruction set architecture comprises one or more types of conditional branch instruction enabling the instruction decoder to control the processing circuitry to set the at least one status value dependent on the transaction nesting depth and perform a conditional branch conditional on the at least one status value being in a target state of the plurality of states, in response to a single transaction nesting depth testing instruction followed by a single conditional branch instruction regardless of whether the target state is the first state, the second state or the third state.

5. The apparatus according to any preceding claim, comprising a condition status storage element to store at least one condition status value indicative of at least one property of a processing result of a previously executed instruction;

wherein in response to decoding of the transaction nesting depth testing instruction by the instruction decoder, the processing circuitry is configured to set said at least one condition status value to correspond with a result of comparing the transaction nesting depth with the predetermined number.

6. The apparatus according to claim 5, wherein in response to decoding of a condition-status-dependent conditional branch instruction by the instruction decoder specifying a test condition, the processing circuitry is configured to perform the conditional branch conditional on whether said at least one condition status value stored in the condition status storage element satisfies the test condition.

7. The apparatus according to any of claims 5 and 6, comprising a plurality of general purpose registers to store operands for instructions;

wherein in response to decoding of the transaction nesting depth testing instruction by the instruction decoder, the processing circuitry is configured to write a transaction nesting depth value representing said transaction nesting depth to a general purpose register specified by the transaction nesting depth testing instruction.

8. The apparatus according to any of claims 1 to 4, comprising a plurality of general purpose registers to store operands for instructions,

wherein in response to decoding of the transaction nesting depth testing instruction by the instruction decoder, the processing circuitry is configured to write the at least one status value to a general purpose register specified by the transaction nesting depth testing instruction.

9. The apparatus according to any of claims 1 to 4 and 8, wherein in the first state, the at least one status value has one of:

a first encoding in which all bits are equal to 0;

a second encoding in which a first predetermined bit is equal to 1 and a second predetermined bit is equal to 0; and

a third encoding in which the first predetermined bit is equal to 0 and the second predetermined bit is equal to 1 .

10. The apparatus according to any of claims 3 and 4, wherein:

in a first one of the first, second and third states, the at least one status value has a first encoding in which all bits are equal to 0;

in a second one of the first, second and third states, the at least one status value has a second encoding in which a first predetermined bit is equal to 1 and a second predetermined bit is equal to 0; and

in a third one of the first, second and third states, the at least one status value has a third encoding in which the first predetermined bit is equal to 0 and the second predetermined bit is equal to 1 .

1 1 . The apparatus according to any preceding claim, wherein in response to the instruction decoder decoding a compare-with-zero type of conditional branch instruction specifying a target register, the processing circuitry is configured to perform the conditional branch conditional on all bits of the target register being equal to 0.

12. The apparatus according to any preceding claim, wherein in response to the instruction decoder decoding a bit-test type of conditional branch instruction specifying a predetermined bit of a target register, the processing circuitry is configured to perform the conditional branch conditional on the predetermined bit of the target register being equal to 1 , or conditional on the predetermined bit of the target register being equal to 0.

13. The apparatus according to any preceding claim, comprising a transaction nesting depth storage element to store a transaction nesting depth value representing said transaction nesting depth.

14. The apparatus according to any preceding claim, wherein the transactional memory support circuitry comprises restoration state storage circuitry to store transaction restoration state captured in response to the transaction start instruction to be restored on aborting the transaction.

15. The apparatus according to claim 14, wherein the processing circuitry is configured to: capture the transaction restoration state in response to the transaction start instruction when the transaction nesting depth equals zero, and

suppress capture of the transaction restoration state in response to the transaction start instruction when the transaction nesting depth is greater than zero.

16. The apparatus according to any preceding claim, wherein the transactional memory support circuitry comprises speculative result storage circuitry to store said results of the speculatively executed instructions for at least one transaction of at least one thread.

17. The apparatus according to any preceding claim, wherein the transactional memory support circuitry comprises conflict detection circuitry to detect a conflict between a data access to a given address made within a transaction of a first thread and a data access to the same address made by another thread.

18. The apparatus according to claim 17, wherein the conflict detection circuitry is configured to trigger said abort event in response to detection of the conflict.

19. The apparatus according to any preceding claim, wherein the transactional memory support circuitry comprises address tracking circuitry to track addresses accessed by instructions within a transaction.

20. A data processing method comprising:

decoding instructions using an instruction decoder; and

performing data processing in response to the instructions decoded by the instruction decoder, using processing circuitry comprising transactional memory support circuitry to support execution of a transaction within a thread of data processing by the processing circuitry, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing circuitry is configured to prevent commitment of results of the speculatively executed instructions of the transaction until the transaction end instruction is reached, and to abort processing of the transaction when an abort event occurs before reaching the transaction end instruction;

in response to decoding of a single transaction nesting depth instruction, setting at least one status value to one of a plurality of states selected dependent on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth equals a predetermined number greater than zero, and at least one further state selected when the transaction nesting depth is greater than or less than the predetermined number; and

in response to decoding of a single conditional branch instruction following the single transaction nesting depth instruction, performing a conditional branch conditional on the at least one status value being in the first state.

21 . A computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of instructions, comprising:

processing program logic to support execution of a transaction within a thread of data processing, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing program logic is configured to prevent commitment of results of the speculatively executed instructions of the transaction until the transaction end instruction is reached, and to abort processing of the transaction when an abort event occurs before reaching the transaction end instruction; and

wherein in response to a transaction nesting depth testing instruction, the processing program logic is configured to set at least one status value to one of a plurality of states selected dependent on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth equals a predetermined number greater than zero, and at least one further state selected when the transaction nesting depth is greater than or less than the predetermined number; and

the processing program logic is configured to support an instruction set architecture comprising at least one type of conditional branch instruction enabling the processing program logic, in response to a single transaction nesting depth testing instruction followed by a single conditional branch instruction, to set the at least one status value dependent on the transaction nesting depth and perform a conditional branch conditional on the at least one status value being in the first state.

22. A storage medium storing the computer program of claim 21 .