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1. (WO2019050773) ULTRA-SHORT DATAGRAMS FOR LATENCY SENSITIVE RADIO FREQUENCY FRONT-END
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CLAIMS

1. A method performed at a device operating as a bus master, comprising:

transmitting a first pulse on a first wire of a multi-wire interface;

transmitting a second pulse on a second wire of the multi-wire interface while the first pulse is present on the first wire of the multi-wire interface, wherein the second pulse is shorter in duration than the first pulse; and

initiating a low-latency mode of communication immediately after termination of the first pulse.

2. The method of claim 1, and further comprising:

configuring a register that defines structure of a datagram to be transmitted during the low-latency mode of communication.

3. The method of claim 2, wherein configuring the register that defines the structure of the datagram includes:

configuring a number of bits to represent a slave device address transmitted in the datagram.

4. The method of claim 3, wherein the slave device address is represented by between 2 and 4 bits.

5. The method of claim 2, wherein configuring the register that defines the structure of the datagram includes:

configuring a number of bits to represent a register address transmitted in the datagram.

6. The method of claim 5, wherein the register address is represented by between 2 and 8 bits.

7. The method of claim 5, and further comprising:

configuring a destination register that identifies a base register in a block of registers to be addressed using the register address in the datagram.

8. The method of claim 2, wherein configuring the register that defines the structure of the datagram includes:

configuring a number of bits to carry a payload in the datagram.

9. The method of claim 8, wherein the payload is carried in between 2 and 8 bits.

10. The method of claim 2, and further comprising:

writing the register that defines the structure of the datagram to at least one slave device.

11. The method of claim 2, and further comprising:

transmitting the datagram using double-data rate encoding.

12. The method of claim 2, and further comprising:

selecting a configuration for a datagram to be transmitted during the low-latency mode of communication,

wherein a difference in durations of the first pulse and the second pulse indicates the selected configuration of the datagram.

13. An apparatus, comprising:

a bus interface adapted to couple the apparatus to a serial bus; and

a processing circuit configured to:

transmit a first pulse on a first wire of a multi-wire interface;

transmit a second pulse on a second wire of the multi-wire interface while the first pulse is present on the first wire of the multi-wire interface, wherein the second pulse is shorter in duration than the first pulse; and initiate a low-latency mode of communication immediately after termination of the first pulse.

14. The apparatus of claim 13, wherein the processing circuit is adapted to:

configure a register that defines structure of a datagram to be transmitted during the low-latency mode of communication.

15. The apparatus of claim 14, wherein the processing circuit is adapted to configure the register that defines the structure of the datagram by:

configuring a number of bits to represent a slave device address or a register address transmitted in the datagram.

16. The apparatus of claim 14, wherein the processing circuit is adapted to configure the register that defines the structure of the datagram by:

configuring a number of bits to carry a payload in the datagram.

17. A method performed at a slave device coupled to a bus, comprising:

detecting a first pulse on a first wire of a multi-wire interface;

detecting a second pulse on a second wire of the multi-wire interface while the first pulse is present on the first wire of the multi-wire interface, wherein the second pulse is shorter in duration than the first pulse; and

entering a low-latency mode of communication immediately after termination of the first pulse.

18. The method of claim 17, and further comprising:

determining a structure of a datagram transmitted during the low-latency mode of communication from bit settings of a first configuration register,

wherein the first configuration register defines a number of bits used to represent an address transmitted in the datagram.

19. The method of claim 18, wherein the first configuration register defines a number of bits used to represent a slave address transmitted in the datagram, and wherein the slave address is represented in a field that has a length of between 2 and 4 bits.

20. The method of claim 18, wherein the first configuration register defines a number of bits used to represent a register address in the datagram, and wherein the register address is represented in a field that has a length of between 2 and 8 bits.

21. The method of claim 20, and further comprising:

using the register address in the datagram to identify a target register in a block of registers, the block of registers commencing at an address identified by a second configuration register; and

writing payload data transmitted in the datagram to the target register.

22. The method of claim 20, and further comprising:

using the register address in the datagram to identify a target register in a block of registers, the block of registers commencing at an address identified by a second configuration register; and

transmitting data read from the target register as payload data in the datagram.

23. The method of claim 18, wherein the first configuration register defines a number of bits used to carry a payload in the datagram.

24. The method of claim 23, wherein the payload is carried in between 2 and 8 bits of the datagram.

25. The method of claim 18, wherein the datagram is transmitted using double-data rate encoding.

26. An apparatus, comprising:

a bus interface adapted to couple the apparatus to a serial bus;

a plurality of configuration registers; and

a processing circuit configured to:

detect a first pulse on a first wire of a multi-wire interface;

detect a second pulse on a second wire of the multi-wire interface while the first pulse is present on the first wire of the multi-wire interface, wherein the second pulse is shorter in duration than the first pulse; and

cause the bus interface to enter a low-latency mode of communication immediately after termination of the first pulse.

27. The apparatus of claim 26, wherein the processing circuit is adapted to:

determine a structure of a datagram transmitted during the low-latency mode of communication from bit settings of a first configuration register,

wherein the first configuration register defines a number of bits used to represent an address transmitted in the datagram.

28. The apparatus of claim 27, wherein the first configuration register defines a number of bits used to represent a slave address or a register address transmitted in the datagram, and wherein the number of bits lies between 2 and 8 bits.

29. The apparatus of claim 27, and further comprising:

a block of bus-accessible registers,

wherein a register address in the datagram is used to identify a target register in a block of bus-accessible registers, the block of bus-accessible registers commencing at an address identified by a second configuration register, and

wherein the processing circuit is adapted to write payload data transmitted in the datagram to the target register.

30. The apparatus of claim 27, and further comprising:

a block of bus-accessible registers, wherein a register address in the datagram is used to identify a target register in a block of bus-accessible registers, the block of bus-accessible registers commencing at an address identified by a second configuration register, and

wherein the processing circuit is adapted to transmit data read from the target register as payload data in the datagram.