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1. (WO2019050653) NANO-POWER CAPACITANCE-TO-DIGITAL CONVERTER
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CLAIMS

What is claimed is:

1. A capacitance-to-digital converter (CDC) comprising:

a comparator having a first input coupled to a sensing electrode and a second input coupled to a reference signal;

a capacitive digital-to-analog converter (DAC) coupled to the first input of the comparator, the capacitive DAC for applying a signal to the sensing electrode; and

a counter for providing control signals to the capacitive DAC, the binary counter receiving logic signals from a logic unit coupled to an output of the comparator,

wherein a capacitance change is detected by a processing unit when a first value of the

counter is substantially different from a second value of the binary counter.

2. The CDC of claim 1, wherein the second value of the counter corresponds to a baseline capacitance of the sensing electrode.

3. The CDC of claim 1, wherein the logic unit determines whether to increment or decrement the counter.

4. The CDC of claim 1, wherein the capacitive DAC comprises a coarse capacitive DAC and a fine capacitive DAC coupled to the output of the counter.

5. The CDC of claim 4, wherein the coarse capacitive DAC comprises a first set of DAC values and the fine capacitive DAC comprises a second set of DAC values, and wherein the first set of DAC values and the second set of DAC values have at least one overlapping value.

6. The CDC of claim 1 further comprising an oscillation loop, the oscillation loop comprising: the comparator;

a first delay element coupled to and output of the comparator;

a second delay element coupled an output of the first delay element; and

a logic element coupled to an output of the second delay element, the logic element for initiating the comparator.

7. The CDC of claim 1 further comprising a zoom capacitor coupled to the first input of the comparator, the zoom capacitor for applying a step signal onto the first input of the comparator.

8. A capacitance-to-digital converter (CDC) comprising:

a comparator having a first input coupled to a first sensing electrode and a second input coupled to a second sensing electrode;

a first capacitive digital-to-analog converter (DAC) coupled to the first input of the

comparator, the capacitive DAC for applying a first signal to the first sensing electrode; a second capacitive digital-to-analog converter (DAC) coupled to the second input of the comparator, the capacitive DAC for applying a second signal to the second sensing electrode; and

a counter for providing control signals to the first and second capacitive DACs, the counter receiving logic signals from a logic unit coupled to an output of the comparator, wherein a capacitance change is detected by a processing unit when a first value of the

counter is substantially different from a second value of the counter.

9. The CDC of claim 8, wherein a first control signal to the first capacitive DAC from the counter is complimentary to a second control signal to the second capacitive DAC from the counter.

10. The CDC of claim 8, wherein the logic unit determines whether to increment or decrement the counter.

11. The CDC of claim 8, wherein the first and second capacitive DACs each comprises a coarse capacitive DAC and a fine capacitive DAC coupled to the output of the counter.

12. The CDC of claim 11, wherein the coarse capacitive DACs comprise a first set of DAC values and the fine capacitive DACs comprises a second set of DAC values, and wherein the first set of DAC values and the second set of DAC values have at least one overlapping value.

13. The CDC of claim 8 further comprising a first zoom capacitor coupled to the first input of the comparator and a second zoom capacitor coupled to the second input of the comparator, the first and second zoom capacitors for applying first and second step signals onto the first and second inputs of the comparator.

14. The CDC of claim 8, wherein the logic unit comprises:

a first inverter coupled between a first output of the comparator and a first input of an OR gate;

a second inverter coupled between a second output of the comparator and a second input of the OR gate; and

a D flip-flop (F/F) coupled to the first input of the OR gate and the output of the OR gate, the D F/F for providing increment or decrement signals to the counter.

15. A method for detecting a change in capacitance on a sensing electrode, the method comprising:

applying a signal to the sensing electrode;

comparing the signal on the sensing electrode to a reference signal;

if the signal on the sensing electrode is less than the reference signal, increasing the signal applied to the sensing electrode;

repeating the steps of applying the signal, comparing the signal, and increasing the signal until the signal is greater than the reference signal;

when the signal is greater than the reference signal, decreasing the signal applied to the

sensing electrode;

if a toggle condition is not detected, repeating the steps of applying the signal, comparing the signal, increasing the signal, and decreasing the signal until a toggle condition is detected; and

storing a first digital value representative of the signal at which the toggle condition is

detected.

16. The method of claim 15, further comprising:

applying a signal corresponding to the stored first digital value to the sensing electrode; and if a toggle condition is detected, determining that no capacitance change has occurred.

17. the method of claim 16 further comprising:

if a toggle condition is not detected, increasing or decreasing the signal until a toggle

condition is detected; and

storing a second digital value representative of the signal at which the toggle condition is detected.

18. The method of claim 17, further comprising:

comparing the second digital value to the first digital value; and

if a difference between the first digital value and the second digital value is great enough, determining that a conductive object is present on the sensing electrode.

19. A method for detecting a change in capacitance of a sensing electrode, the method comprising:

applying a first, predetermined signal to the sensing electrode;

comparing a resultant signal derived from the first predetermined signal and a capacitance of the sensing electrode to a reference signal; and

if the resultant signal is substantially similar to the reference signal, determining no

capacitance change of the sensing electrode.

20. The method of claim 19, further comprising:

if the resultant signal is not substantially similar to the reference signal, applying a second signal to the sensing electrode;

comparing a resultant signal derived from the second signal and a capacitance of the sensing electrode to a reference signal; and

quantifying the change in capacitance by comparing the second signal and the first

predetermined signal.