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1. (WO2019005148) FLOATING GATE TRANSISTOR
国际局存档的最新著录项目数据    提交意见

公布号: WO/2019/005148 国际申请号: PCT/US2017/040476
公布日: 03.01.2019 国际申请日: 30.06.2017
国际专利分类:
H01L 27/11 (2006.01) ,H01L 21/8234 (2006.01) ,H01L 29/423 (2006.01)
H 电学
01
基本电气元件
L
半导体器件;其他类目中不包括的电固体器件
27
由在一个共用衬底内或其上形成的多个半导体或其他固态组件组成的器件
02
包括有专门适用于整流、振荡、放大或切换的半导体组件并且至少有一个电位跃变势垒或者表面势垒的;包括至少有一个跃变势垒或者表面势垒的无源集成电路单元的
04
其衬底为半导体的
10
在重复结构中包括有多个独立组件的
105
包含场效应组件的
11
静态随机存取存储结构的
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H 电学
01
基本电气元件
L
半导体器件;其他类目中不包括的电固体器件
29
专门适用于整流、放大、振荡或切换,并具有至少一个电位跃变势垒或表面势垒的半导体器件;具有至少一个电位跃变势垒或表面势垒,例如PN结耗尽层或载流子集结层的电容器或电阻器;半导体本体或其电极的零部件
40
按其电极特征区分的
41
以其形状、相对尺寸或位置为特征的
423
不通有待整流、放大或切换电流的
申请人:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd Santa Clara, California 95054, US
发明人:
MORRIS, Daniel; US
AVCI, Uygar; US
YOUNG, Ian; US
代理人:
MUGHAL, Usman; US
优先权数据:
标题 (EN) FLOATING GATE TRANSISTOR
(FR) TRANSISTOR À GRILLE FLOTTANTE
摘要:
(EN) Described is an apparatus which comprises: a first transistor coupled to a power supply node; a memory bit-cell; and a second transistor coupled to the memory bit-cell and the first transistor, wherein the second transistor comprises a gate which is independent of an ohmic contact and is controlled by charging or discharging a conductor which is at least partially around the gate.
(FR) L'invention concerne un appareil qui comprend : un premier transistor couplé à un nœud d'alimentation électrique; une cellule binaire de mémoire; et un second transistor couplé à la cellule binaire de mémoire et au premier transistor, le second transistor comprenant une grille qui est indépendante d'un contact ohmique et qui est commandée par charge ou décharge d'un conducteur qui est au moins partiellement autour de la grille.
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指定国: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
非洲地区知识产权组织 (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
欧亚专利局 (AM, AZ, BY, KG, KZ, RU, TJ, TM)
欧洲专利局 (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
非洲知识产权组织 (OAPI) (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
公布语言: 英语 (EN)
申请语言: 英语 (EN)