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1. (WO2019066953) GROUP III-NITRIDE (III-N) DEVICES WITH REDUCED CONTACT RESISTANCE AND THEIR METHODS OF FABRICATION
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Claims

What is claimed is:

1. A device comprising:

a terminal structure comprising a first group Ill-Nitride (III-N) material, the terminal structure having a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins;

a polarization charge inducing layer above the terminal structure, the polarization charge inducing layer comprising a second III-N material;

a gate electrode above the polarization charge inducing layer;

a source structure on the polarization charge inducing layer above a second portion of the central body and on sidewalls of the first plurality of fins, wherein the source structure comprises a third III-N material;

a drain structure on the polarization charge inducing layer, above a third portion of the central body and on sidewalls of the second plurality of fins, wherein the drain structure comprises the third III-N material;

a source contact on the source structure; and

a drain contact on the first and second portions of the drain structure.

2. The semiconductor structure of claim 1, wherein each fin in the first or the second plurality of fins has a width between lOOnm - 500nm and a length between 0.5 micrometer and 1 micrometer.

3. The semiconductor structure of claim 2, where a spacing between each successive fin in the first or the second plurality of fins is less than the width of the fin.

4. The device of claim 2, wherein the number of fins in the first and the second plurality of fins is between 2-1000.

5. The semiconductor structure of any of claims 1-4, wherein the source contact has an area of contact on the source structure, wherein the area of contact has a first dimension that is greater than a combined width of the first plurality of fins and the combined width of the spacing between the first plurality of fins and, wherein the source contact has a second dimension that is approximately equal to the length of the first plurality of fins.

6. The semiconductor structure of any of claims 1-4, wherein the drain contact has an area of contact on the drain structure, wherein the area of contact has a first dimension that is greater than a combined width of the second plurality of fins and the combined width of the spacing between the second plurality of fins and, wherein the drain contact has a second dimension that is approximately equal to the length of the second plurality of fins.

7. The semiconductor structure of any of claims 1-6, wherein the source contact is in contact with all upper surfaces of the source structure and the drain contact is in contact with all upper surfaces of the drain structure.

8. The semiconductor structure of claim 1, wherein the source structure covers an interface between the polarization charge inducing layer and the first III-N material, and the drain structure covers an interface between the polarization charge inducing layer and the first III-N material.

9. The semiconductor structure of claim 1, wherein the source structure and a drain structure comprise of faceted crystals having sidewalls that are approximately 60 degrees with respect to an uppermost surface of the first or the second plurality of fins.

10. The device of any of claims 1-9, wherein the sidewalls meet to form an apex.

11. The semiconductor of any of claims 1-9, wherein the source structure and a drain structure each have an uppermost surface that is corrugated and wherein the corrugation is between lOnm-50nm.

12. The semiconductor structure of claim 1, wherein the first III-N material includes a gallium nitride (GaN) and the second III-N material includes a III-N material that includes aluminum.

13. The semiconductor structure of claim 1, wherein the source structure and the drain structure each include a material that is lattice matched to the first group Ill-nitride (III-N) semiconductor material.

14. The semiconductor structure of claim 1, wherein the impurity dopant includes an n-type impurity dopant.

15. The semiconductor structure of claim 1, wherein the source structure and the drain structure each comprises a III-N material having an indium content that increases from 1% to 10%.

16. The semiconductor structure of claim 1 further includes a gate dielectric layer between the gate electrode and the polarization charge inducing layer.

17. The semiconductor structure of claim 1, wherein the gate electrode comprises a work function layer and a gate metal cap.

18. A method of fabricating a semiconductor structure, the method comprising:

forming a layer comprising a first group Ill-nitride (III-N) material on a substrate;

forming a polarization charge inducing layer comprising a second III-N material above the first layer;

patterning the layer comprising the first III-N material and the polarization charge inducing layer and forming a central body, a first plurality of fins adjacent to a first side of the central body, and a second plurality of fins adjacent to a second side of the central body, opposite the first side;

forming an isolation between the first plurality of fins and between the second plurality of fins;

forming a source structure in the first recess and a drain structure in the second recess;

forming a gate dielectric layer on the polarization charge inducing layer;

forming a gate electrode on the gate dielectric layer; and

forming a source contact on the source structure and a drain contact on the drain structure

19. The method of claim 18, wherein forming the isolation comprises:

depositing an electrically insulating layer on the patterned polarization charge inducing layer, between the first and the second plurality of fins and on the layer comprising the first III-N material between the first and the second plurality of fins;

planarizing the electrically insulating layer and removing it from an uppermost surface of the polarization charge inducing layer; and

recessing the electrically insulating layer by a wet chemical technique, wherein the recessing exposes an upper portion of the first III-N material.

20. The method of claim 18, wherein forming the source structure comprises:

forming a mask structure on a portion of the central body, the forming separating a first portion of a central body from a second portion of the central body; and

growing a third III-N material on the first plurality of fins and on the first portion of the central body and forming the drain structure comprises growing the third III-N material on the second plurality of fins and on the second portion of the central body, wherein the process of growing leads to the formation of crystal structures with slanted sidewalls.

21. The method of claim 20, wherein process of growing the third III-N material comprises growing to merge the slanted sidewalls to form an apex.

22. The method of claim 20, wherein process of growing the third III-N material further comprises forming the third III-N material on portions of exposed sidewalls of the patterned polarization charge inducing layer and the first III-N material

23. A system comprising:

a processor; and

a radio transceiver coupled to the processor, wherein the radio transceiver includes a transistor comprising:

a first structure comprising a first III-N material, the first structure comprising a central body and a first plurality of fins adjacent to a first side of the central body, a second plurality of fins adjacent to a second side of the central body, opposite the first side;

a polarization charge inducing layer above a first portion of the central body, the polarization charge inducing layer comprising a second III-N material;

a gate electrode above the polarization charge inducing layer; and a source structure and a drain structure comprising a third III-N material with an impurity dopant on opposite sides of the gate electrode, the source structure above a second portion of the central body and above the first plurality of fins, the drain

structure above a third portion of the central body and above the second plurality of fins; and

a source contact on the first and second portions of the source structure; and a drain contact on the first and second portions of the drain structure.

24. The device of claim 2, wherein the number of fins in the first and the second plurality of fins is between 2-1000.

25. The semiconductor structure of claim 1, wherein the source contact has an area of contact on the source structure, wherein the area of contact has a first dimension that is greater than a combined width of the first plurality of fins and the combined width of the spacing between the first plurality of fins and, wherein the source contact has a second dimension that is

approximately equal to the length of the first plurality of fins.