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1. (WO2019046111) MEMORY ARRAY ACCESSIBILITY
Nota: O texto foi obtido por processos automáticos de reconhecimento ótico de caracteres.
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What is claimed is:

1. An apparatus, comprising:

an array of memory cells, wherein the array comprises:

a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus;

a second portion accessible to the devices external to the apparatus; and

a number of registers configured to store row addresses that indicate which portion of the array is the first portion; and

the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

2. The apparatus of claim 1 , wherein the number of registers comprise access control registers.

3. The apparatus of claim 2, wherein the access control registers comprise row access control registers.

4. The apparatus of claim 1, wherein the controller is configured to:

allow execution of instructions stored in the first portion to write to or read from the second portion; and

not allow instructions to be executed from the second portion.

5. The apparatus of claim 1, wherein the number of registers are only writeable by instructions executed from the first portion.

6. The apparatus of claim 1, wherein the controller is configured to allow data to be copied into the first portion only by running the instructions executed from the first portion.

7. The apparatus of claim 1, wherein the controller is configured to prevent external DRAM ACT commands from executing inside the first portion in response to the registers being loaded.

8. The apparatus of claim 1, wherein the controller is configured to prevent internal PIM instruction commands from executing external to the first portion in response to the registers being loaded.

9. The apparatus of claim 1, wherein the controller is configured to allow instructions to be executed from the second portion only in response to the instructions having no target in the first portion.

10. The apparatus of claim 1, wherein the controller is configured to prevent data from being copied from the first portion to the second portion in response to execution of an instruction that is not stored in the first portion.

11. The apparatus of claim 1, wherein the controller is configured to prevent data from being copied from the second portion to the first portion in response to execution of an instruction that is not stored in the first portion.

12. The apparatus of any one of claims 1 to 11 , wherein the apparatus is a processor-in-memory (PIM) device that comprises:

the array of the memory cells; and

the controller;

wherein the array and the controller are on a same die.

13. The apparatus of claim 12, wherein a host is coupled to the PIM device and is one of the devices external to the apparatus.

14. The apparatus of any one of claims 1 to 11 , wherein the number of registers are configured to each store an address associated with a row of the array.

15. The apparatus of claim 14, wherein the portion of the array between the addresses stored in each of the number of registers is the first portion.

16. The apparatus of claim 14, wherein, in response to the addresses associated with each of the number of registers being modified, the first portion of the array is modified.

17. An apparatus, comprising:

an array of memory cells, comprising:

a first portion of memory cells that are inaccessible by devices external to the apparatus and that are configured to store a first set of data and a set of instructions;

a second portion of memory cells that are accessible by the devices external to the apparatus and that are configured to store a second set of data; and

a set of address registers, wherein the set of address registers indicate which portion of the array is the inaccessible first portion; and

a controller configured to execute the first set of instructions in the inaccessible first portion.

18. The apparatus of claim 17, wherein the accessible second portion comprises an additional set of instructions that are executed, by the controller, without reading or writing data into the first inaccessible portion of memory cells.

19. The apparatus of claim 17, wherein the controller is configured to transfer data from the inaccessible first portion to the accessible second portion.

20. The apparatus of any one of claims 17 to 19, wherein the controller is configured to recognize data written to the accessible second portion as operands and to not recognize the data as instructions.

21. The apparatus of any one of claims 17 to 19, wherein the controller is configured to recognize data written to the inaccessible first portion as one of operands and the set of instructions.

22. The apparatus of claim 21, wherein the controller is configured to execute the set of instructions in the inaccessible first portion.

23. The apparatus of claim 20, wherein the accessible second portion of memory cells are configured to store a second set of instructions, wherein the second set of instructions are executed without reading or writing data into the first inaccessible portion of memory cells.

24. A method, comprising:

reading addresses in a number of registers;

identifying a first portion of an array of memory cells indicated by the read addresses;

executing instructions, stored in the first portion, within memory cells of the first portion;

preventing access to the first portion; and

allowing access to a second portion of the array.

25. The method of claim 24, comprising modifying the address in the number of registers that modifies which memory cells of the array that make up the first portion.

26. The method of any one of claims 24 to 25, wherein a first address of a first of the number of registers indicates a first row of cells of the first portion.

27. The method of claim 26, wherein a second address of a second of the number of registers indicates a last row of cells of the first portion.

28. The method of claim 26, comprising:

decrypting data as the data is initially read and written into the first portion; and

leaving the data unencrypted in the first portion.

29. The method of any one of claims 24 to 25, comprising clearing data from the first portion in response to a system reset being performed.

30. The method of claim 29, comprising clearing the number of registers in response to the system reset being performed.