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1. (WO2017175801) POLYCRYSTALLINE CERAMIC SUBSTRATE, POLYCRYSTALLINE CERAMIC SUBSTRATE PROVIDED WITH BONDING LAYER, AND LAMINATED SUBSTRATE
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№ de pub.:    WO/2017/175801    № do pedido internacional:    PCT/JP2017/014255
Data de publicação: 12.10.2017 Data de depósito internacional: 05.04.2017
CIP:
C30B 33/06 (2006.01), C04B 37/00 (2006.01), H01L 21/02 (2006.01)
Requerentes: SUMITOMO ELECTRIC INDUSTRIES, LTD. [JP/JP]; 5-33, Kitahama 4-chome, Chuo-ku, Osaka-shi, Osaka 5410041 (JP)
Inventores: GESHI Keiichiro; (JP).
NAKAYAMA Shigeru; (JP).
YOSHIMURA Masashi; (JP)
Mandatário: NAKATA Motomi; (JP).
MORITA Takeshi; (JP).
TAKAGI Masahiro; (JP).
OGATA Daisuke; (JP)
Dados da prioridade:
2016-077130 07.04.2016 JP
Título (EN) POLYCRYSTALLINE CERAMIC SUBSTRATE, POLYCRYSTALLINE CERAMIC SUBSTRATE PROVIDED WITH BONDING LAYER, AND LAMINATED SUBSTRATE
(FR) SUBSTRAT CÉRAMIQUE POLYCRISTALLIN, SUBSTRAT CÉRAMIQUE POLYCRISTALLIN POURVU D’UNE COUCHE DE LIAISON ET SUBSTRAT STRATIFIÉ
(JA) 多結晶セラミック基板、接合層付き多結晶セラミック基板および積層基板
Resumo: front page image
(EN)Provided is a polycrystalline ceramic substrate bonded to a compound semiconductor substrate via a bonding layer, wherein relational expression (1) 0.7 < α12 < 0.9 … (1) and/or relational expression (2) 0.7 < α34 < 0.9 … (2) is established, where the coefficient of linear expansion of the polycrystalline ceramic substrate is α1 and the coefficient of linear expansion of the compound semiconductor substrate is α2 at 30-300°C, and the coefficient of linear expansion of the polycrystalline ceramic substrate is α3 and the coefficient of linear expansion of the compound semiconductor substrate is α4 at 30-1000°C.
(FR)L’invention concerne un substrat céramique polycristallin lié à un substrat semi-conducteur composé par l’intermédiaire d’une couche de liaison, l'expression de relation (1) 0,7 < 12 < 0,9… (1) et/ou l'expression de relation (2) 0,7 < α34 < 0,9… (2) étant satisfaites, le coefficient de dilatation linéaire du substrat céramique polycristallin étant α1 et le coefficient de dilatation linéaire du substrat semi-conducteur composé étant α2 à une température allant de 30 à 300 °C, le coefficient de dilatation linéaire du substrat céramique polycristallin étant α3 et le coefficient de dilatation linéaire du substrat semi-conducteur composé étant α4 à 30 à 1000 °C.
(JA)化合物半導体基板に対して接合層を介して接合される多結晶セラミック基板においては、30℃~300℃における、多結晶セラミック基板の線膨張係数をα、化合物半導体基板の線膨張係数をαとし、30℃~1000℃における、多結晶セラミック基板の線膨張係数をα、化合物半導体基板の線膨張係数をαとした場合に、関係式(1) 0.7<α/α<0.9・・・(1) および関係式(2) 0.7<α/α<0.9・・・(2) のうち少なくともいずれか一方が成立する。
Estados designados: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Língua de publicação: Japanese (JA)
Língua de depósito: Japanese (JA)