Pesquisa nas coleções internacionais e nacionais de patentes
Algum conteúdo deste aplicativo está indisponível no momento.
Se esta situação persistir, por favor entre em contato conoscoFale conosco & Contato
1. (WO1998028745) NONVOLATILE WRITEABLE MEMORY WITH FAST PROGRAMMING CAPABILITY
Nota: O texto foi obtido por processos automáticos de reconhecimento ótico de caracteres.
Para fins jurídicos, favor utilizar a versão PDF.

CLAIMS
WHAT IS CLAIMED IS:

1. A method of programming a nonvolatile writeable memory, the method comprising the steps of:
(a) programming one or more memory cells of a block of memory cells of the nonvolatile writeable memory, wherein no more than one program pulse is used to program any one memory cell;
(b) identifying memory cells of the block of memory cells having a threshold voltage in an intermediate region below a programmed
reference level and above an erased reference level ; and
(c) providing one or more program pulses to each of the memory cells identified in the step (b) to raise the threshold voltage up to the programmed reference level.

2. The method of claim 1, wherein the intermediate region is above the erased reference level by approximately 300 mV to 500 mV, wherein erased memory cells have a threshold voltage below the erased reference level.

3. In a nonvolatile writeable memory having a program verify capability, a method of programming the nonvolatile writeable memory comprising the steps of:
(a) programming a block of memory cells of the nonvolatile writeable memory using an initial program cycle having a predetermined latency;

(b) checking each of the block of memory cells to determine whether any of the memory cells have a threshold voltage in an intermediate region above an erased reference level but below a programmed
reference level; and
(c) programming each of the block of memory cells found in the intermediate region up to the programmed reference level.

4. In a nonvolatile writeable memory having a program verify capability, a method of programming the nonvolatile writeable memory comprising the steps of: (a) programming a block of memory cells of the nonvolatile writeable memory without using the program verify to determine whether each memory cell was programmed to a programmed reference level ;
(b) checking each of the block of memory cells to determine whether any of the memory cells were programmed above an erased reference level but not programmed above the programmed reference level ; and
(c) programming each of the block of memory cells found in the step (b) to the programmed reference level.

5. The method of claim 4, wherein the nonvolatile writeable memory performs the steps (a) - (c) responsive to a signal provided to a pin of the nonvolatile writeable memory.

6. The method of claim 4, wherein the nonvolatile writeable memory performs the steps (a) - (c) responsive to a command written to the nonvolatile writeable memory.

7. The method of claim 4, wherein the step (a) is performed on all of the memory cells of the nonvolatile writeable memory prior to step (b) being performed.

8. In a nonvolatile writeable memory having program verify capability, a method of programming the nonvolatile writeable memory comprising the steps of:
(a) programming a block of memory cells of the nonvolatile writeable memory at a first data rate, wherein the first data rate allows no more than one program pulse to be used to program a memory cell of the
nonvolatile writeable memory;
(b) identifying a subset of the memory cells programmed in the step (a) that have a threshold voltage above a fast programming reference level but below a programmed reference level, wherein the fast
programming reference level corresponds to an erased reference level plus a guardband; and (c) programming the memory cells identified in the step (b) until they are above the programmed reference level.

9. The method of claim 8 wherein the guardband is approximately 300 mV to 500 mV.

10. A nonvolatile writeable memory capable of being programmed in a first mode and a second mode, the nonvolatile writeable memory comprising:
a memory array; and
a control engine, wherein in the first mode, the control engine programs the memory array one memory cell at a time, wherein after each memory cell is programmed it is checked to determine whether it is programmed above a programmed reference level, and if it is not programmed over the programmed reference level, then it is provided with one or more program pulses until it has a threshold voltage over the programmed reference level, and wherein in the second mode, the control engine programs a block of memory cells of the memory array, wherein each memory cell of the block of memory cells is programmed with a single program pulse, and subsequently if any of the memory cells that was programmed with the single program pulse has a threshold voltage below the programmed reference level, that memory cell is programmed with one or more program pulses until it has a threshold voltage over the programmed reference level.

11. The nonvolatile writeable memory of claim 10 further comprising: a command interface capable of decoding a fast program command that signals the control engine to program the memory array using the second mode.

12. The nonvolatile writeable memory of claim 10 further comprising: a fast program pin, wherein a signal provided via the fast program pin indicates to the control engine to program the memory array using the second mode.