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1. (WO2019024803) LEVEL SHIFTER CIRCUIT AND INTEGRATED CIRCUIT CHIP
국제사무국에 기록된 최신 서지정보정보 제출

공개번호: WO/2019/024803 국제출원번호: PCT/CN2018/097533
공개일: 07.02.2019 국제출원일: 27.07.2018
IPC:
H03K 19/0185 (2006.01)
H SECTION H — 전기
03
기본전자회로
K
펄스(PULSE)기술
19
논리회로, 즉 1출력에 작용하는 적어도 2입력이 있는 것; 쌍전(inverting)회로
0175
결합장치, 인터페이스장치
0185
오직 전계효과 트랜지스터만 사용하는 것
출원인:
深圳市中兴微电子技术有限公司 SANECHIPS TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 南山区西丽街道留仙大道中兴工业园 ZTE Industrial Park, Liuxian Avenue Xili Street, Nanshan District Shenzhen, Guangdong 518055, CN
발명자:
党涛 DANG, Tao; CN
대리인:
北京天昊联合知识产权代理有限公司 TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS; 中国北京市 东城区建国门内大街28号民生金融中心D座10层张帆 Fan Zhang, 10th Floor, Tower D Minsheng Financial Center 28 Jianguomennei Avenue Dongcheng District, Beijing 100005, CN
우선권 정보:
201710639905.731.07.2017CN
발명의 명칭: (EN) LEVEL SHIFTER CIRCUIT AND INTEGRATED CIRCUIT CHIP
(FR) CIRCUIT DE DÉCALAGE DE NIVEAU ET PUCE DE CIRCUIT INTÉGRÉ
(ZH) 电平移位电路和集成电路芯片
요약서:
(EN) Provided in the present disclosure are a level shifter circuit and an integrated circuit chip. In said level shifter circuit, access voltage division circuits are additionally arranged between the drain of a P-channel metal oxide semiconductor field effect transistor (PMOS) and the drain of an N-channel metal oxide semiconductor field effect transistor (NMOS), between the source and drain of the PMOS and between the source and drain of the NMOS respectively within a level shifter circuit composed of a first PMOS and a second PMOS that are cross-connected and a first NMOS and a second NMOS that serve as two low voltage domain inversion signal inputs.
(FR) La présente invention concerne un circuit de décalage de niveau et une puce de circuit intégré. Dans ledit circuit de décalage de niveau, des circuits de division de tension d'accès sont agencés de manière complémentaire entre le drain d'un transistor à effet de champ à semi-conducteur à oxyde métallique à canal P (PMOS) et le drain d'un transistor à effet de champ à semi-conducteur à oxyde métallique à canal N (NMOS), entre la source et le drain du PMOS et entre la source et le drain du NMOS respectivement dans un circuit de décalage de niveau composé d'un premier PMOS et d'un second PMOS qui sont connectés en croix et d'un premier NMOS et d'un second NMOS qui servent en tant que deux entrées de signal d'inversion de domaine basse tension.
(ZH) 本公开提供了一种电平移位电路和一种集成电路芯片。在所述电平移位电路中,在由交叉连接的第一P沟道场效应晶体管(PMOS)和第二PMOS以及作为两个低电压域反相信号输入的第一N沟道场效应晶体管(NMOS)和第二NMOS组成的电平移位电路中,在PMOS的漏极和NMOS的漏极之间、PMOS源极和漏极之间和NMOS源极和漏极之间分别增加设置接入分压电路。
front page image
지정국: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
아프리카지역 지식재산권기구(ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
유라시아 특허청(EAPO) (AM, AZ, BY, KG, KZ, RU, TJ, TM)
유럽 특허청(EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
아프리카 지식재산권기구(OAPI) (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
공개언어: 중국어 (ZH)
출원언어: 중국어 (ZH)