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1. (WO2019001896) ADDRESS TRANSLATION DATA INVALIDATION
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CLAIMS

1 . Apparatus for processing data comprising:

one or more translation buffers to store respective address translation data to map received addresses to translated addresses; and

processing circuitry to execute program instructions; wherein

said processing circuitry is responsive to a translation buffer invalidation instruction within a sequence of program instructions executing using a given address translation context to broadcast translation buffer invalidation signals to said one or more translation buffers, and

said translation buffer invalidation signals specify said given address translation context.

2. Apparatus as claimed in claim 1 , wherein said apparatus supports execution of a plurality of virtual machine execution contexts and said given address translation context includes a virtual machine identifier to identify a virtual machine execution context of said translation buffer invalidation instruction.

3. Apparatus as claimed in any one of claims 1 and 2, wherein said apparatus supports execution of a plurality of processes having respective address space translation mappings and said given address translation context includes an address space identifier to identify a process of said translation buffer invalidation instruction among said plurality of processes.

4. Apparatus as claimed in any one of the preceding claims, wherein a given translation buffer among said one or more translation buffers stores given buffer context data specifying an address translation context of given address translation data stored within said given translation buffer.

5. Apparatus as claimed in claim 4, comprising context comparison circuitry associated with said given translation buffer to perform a comparison of said given buffer context data with said signals specify said given address translation context.

6. Apparatus as claimed in claim 5, wherein

when said given buffer context data matches said signals specify said given address translation context, said comparison circuitry permits flushing of said given address translation data, and

when said given buffer context data differs from said signals specify said given address translation context, said comparison circuitry inhibits flushing of said given address translation data.

7. Apparatus as claimed in any one of claims 4, 5 and 6, wherein

said processing circuitry comprises a processing element using said given address translation data stored within said given translation buffer,

said processing element supports transactional memory accesses whereby a transaction comprising program instructions bounded by a transaction start point and a transaction commit point is atomically executed and may be aborted prior to reaching said transaction commit point and return said apparatus to a state corresponding to said transaction start point, and

said processing element selectively aborts a pending transaction in dependence upon said comparison.

8. Apparatus as claimed in claim 7, wherein said processing element continues with said pending transaction when said given buffer context data differs from said signals specify said given address translation context.

9. Apparatus as claimed in any one of claims 7 and 8, wherein

said translation buffer invalidation signals specify one or more target received address values for which address translation data is to be invalidated;

said given translation buffer comprises range tracking circuitry to track a minimum address value and a maximum address value accessed by said processing element during use of said given translation data stored within said given translation buffer, and

said processing element continues with said pending transaction when said one or more target received address values are outside a range bounded by said minimum address value and said maximum address value.

10. Apparatus as claimed in claim 9, wherein said processing element aborts said pending transaction when both said given buffer context data matches said signals specify said given address translation context and said one or more target received address values are within a range bounded by said minimum address value and said maximum address value.

1 1 . Apparatus as claimed in any one of claims 9 and 10, wherein said precessing element supports interleaved execution of a plurality of program threads and said given translation buffer stores, for each of said plurality of program threads, given buffer context data and range tracking data characterising said minimum address value and said maximum address value.

12. Apparatus as claimed in any one of claims 7 to 1 1 , wherein said processing element comprises one of a general purpose processor, and a graphics processing unit.

13. Apparatus as claimed in any one of the preceding claims, wherein said address translation data provides one of:

a mapping of virtual addresses to physical addresses; and

a mapping of virtual addresses to intermediate physical addresses.

14. Apparatus as claimed in any one of the preceding claims, wherein said one or more translation buffers comprise one or more translation lookaside buffers.

15. Apparatus for processing data comprising:

one or more translation buffers means for storing respective address translation data to map received addresses to translated addresses; and

processing means for executing program instructions; wherein

said processing means is responsive to a translation buffer invalidation instruction within a sequence of program instructions executing using a given address translation context to broadcast translation buffer invalidation signals to said one or more translation buffers, and

said translation buffer invalidation signals specify said given address translation context.

16. A method of processing data comprising:

storing within one of more translation buffers respective address translation data to map received addresses to translated addresses; and

executing program instructions; wherein

in response to a translation buffer invalidation instruction within a sequence of program instructions executing using a given address translation context, broadcasting translation buffer invalidation signals to said one or more translation buffers, and

said translation buffer invalidation signals specify said given address translation context.

17. A computer program for controlling a host data processing apparatus to provide an instruction execution environment comprising:

one or more translation buffer data structures to store respective address translation data to map received addresses to translated addresses; and

processing program logic to execute program instructions; wherein

said processing program logic is responsive to a translation buffer invalidation instruction within a sequence of program instructions executing using a given address translation context to broadcast translation buffer invalidation signals to said one or more translation buffer data structures, and

said translation buffer invalidation signals specify said given address translation context.

18. A storage medium storing the computer program of claim 17.