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1. (WO2013095343) GROUP III-N NANOWIRE TRANSISTORS
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CLAIMS

What is claimed is:

1. A group III-N transistor, comprising:

a nanowire disposed on a substrate, wherein a longitudinal length of the nanowire further comprises:

a channel region of a first group III-N material;

a source region electrically coupled with a first end of the channel region; and a drain region electrically coupled with a second end of the channel region, a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region, and

a second group III-N material disposed between the first group III-N material and gate stack along at least a portion of the channel region.

2. The group III-N transistor of claim 1, wherein the second group III-N material is to provide a back barrier with a heteroj unction formed along a first surface of the nanowire, and to induce a 2DEG within the channel region with a heteroj unction along a second surface of the nanowire.

3. The group III-N transistor of claim 1, wherein the first surface is along a top surface of the nanowire, opposite the substrate, and wherein the second surface is along a bottom surface sidewall, opposite the top surface.

4. The group III-N transistor of claim 1, wherein the nanowire is disposed within a vertical stack of nanowires, wherein each of nanowires has a channel region consisting essentially of the first group III-N material, and wherein at least two of the plurality of nanowires are physically coupled together at a point along the longitudinal length by a third crystalline semiconductor material different than the first group III-N material.

5. The group III-N transistor of claim 4, wherein the third semiconductor has a larger bandgap than that of the first group III-N material.

6. The group III-N transistor of claim 5, wherein the first and third semiconductor

materials comprise an epitaxial stack, wherein the nanowires each have a longitudinal axis extending parallel to the substrate.

7. The group III-N transistor of claim 1, wherein the drain region is separated from the channel region by an extrinsic drain region comprising a third group III-N material having a wider bandgap than that of the first group III-N material.

8. The high voltage transistor of claim 7, wherein the extrinsic drain region is an alloy of the first and third group III-N materials with a bandgap intermediate between those of the first and third group III-N materials.

9. The group III-N transistor of claim 7, wherein the source region is spaced apart from the channel region by a first longitudinal length, and wherein the extrinsic drain region has a second longitudinal length, greater than the first longitudinal length.

10. The group III-N transistor of claim 1, further comprising:

a drain contact coaxially wrapping completely around the drain region; and a source contact coaxially wrapping completely around the source region.

11. The group III-N transistor of claim 1 , wherein the first group III-N material consists essentially of GaN, or consists essentially of InN, or consists essentially of AlxIni_xN, where x is less than 1, or consists essentially of AlxGai_xN, where x is less than 1.

12. The group III-N transistor of claim 11, wherein the second group III-N comprises A1N, GaN, AlyIni_yN, or AlyGai_xN, where y is greater than x.

13. The group III-N transistor of claim 12, wherein the third group III-N comprises A1N, GaN, InN, AlzIni_zN, or AlzGai_zN, where z is different than x.

14. The group III-N transistor of claim 13, wherein the drain region consists essentially of the first group III-N material.

15. A method of forming a group III-N transistor on a substrate, the method comprising: epitaxially growing a stack of semiconductor materials on the substrate, the stack

comprising at least a first group III-N material;

etching the stack to define a nanowire;

epitaxially growing a second group III-N material on the first group III-N material along a channel region of the nanowire; and

forming a gate conductor coaxially wrapping completely around the first

semiconductor and over the second group III-N material, along a longitudinal channel length of the nanowire.

16. The method of claim 15, wherein etching the stack further comprises removing a third semiconductor material selectively relative to the first group III-N material to form a gap between the first group III-N material and the substrate along the longitudinal channel length; wherein epitaxially growing the second group III-N material further comprises growing the second group III-N material on a surface of the first group III-N material exposed by the gap; and

wherein forming gate conductor further comprises backfilling the gap with the gate insulator and gate conductor along the longitudinal channel length.

17. The method of claim 15, wherein epitaxially growing the stack of semiconductor materials further comprises growing the first group III-N material on a third group III-N material, and wherein removing the third semiconductor material selectively to the first group III-N material further comprises removing the third group III-N material to undercut the first group III-N material.

18. The method of claim 17, wherein epitaxially growing the first group III-N material further comprises epitaxially growing a material consisting essentially of GaN, or consisting essentially of InN, or consisting essentially of AlxIni_xN, where x is less than 1, or consisting essentially of AlxGai_xN, where x is less than 1 ; and

wherein epitaxially growing the third group III-N comprises epitaxially growing A1N, GaN, AlzIni_zN, or AlzGai_zN, where z is different than x.

19. The method of claim 18, wherein epitaxially growing the second group III-N material further comprises growing A1N, GaN, AlyIni_yN, where y is greater than x, or AlyGai_xN, where y is greater than x.

20. The method of claim 17, further comprising:

thermal annealing at a temperature sufficient to intermix the first and third group III-N materials remaining as an epitaxial stack after forming the gate conductor.

21. The method of claim 15, further comprising:

forming a drain contact coaxially wrapping completely around the first group III-N along a drain region of the nanowire; and

forming a source contact coaxially wrapping completely around the first group III-N along source region of the nanowire.

22. The method of claim 21, wherein forming drain contact, and source contact, further comprises:

removing the third group III-N material selectively to the first group III-N material to form a second gap between the first group III-N and the substrate along each of the source and drain regions; and

backfilling the second gap with an ohmic metal.

23. A system on chip (SoC), comprising:

a power management integrated circuit (PMIC) including at least one of a switching voltage regulator or switching mode DC-DC converter; and

an RF integrated circuit (RFIC) including a power amplifier operable to operate with a cut-off frequency, Ft and maximum oscillation frequency, Fmax of both at least 20 GHz, and generate a carrier wave frequency of at least 2 GHz, wherein both of the PMIC and RFIC are monolithically integrated onto a same substrate, and wherein at least one of PMIC and RFIC include the high voltage transistor of claim 1.

24. The SoC of claim 23, further comprising:

a controller of at least one of the PMIC and RFIC integrated onto the substrate, wherein the controller comprises CMOS technology fabricated with silicon field effect transistors.

25. A mobile computing device, comprising:

a touchscreen;

a battery;

an antenna; and

the SoC of claim 23, wherein the PMIC is coupled to the battery and wherein the RFIC is coupled to the antenna.

26. The mobile computing device of claim 25, further comprises a first and second processor core, each core operably coupled to the touchscreen, the PMIC and RFIC, wherein the first and second processor cores comprise CMOS technology fabricated with silicon field effect transistors.