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1. (US20130279145) Group III-N nanowire transistors
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Claims

1. A group III-N transistor, comprising:
a nanowire disposed on a substrate, wherein a longitudinal length of the nanowire further comprises:
a channel region of a first group III-N material;
a source region electrically coupled with a first end of the channel region; and
a drain region electrically coupled with a second end of the channel region,
a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region, and
a second group III-N material disposed between the first group III-N material and gate stack along at least a portion of the channel region.
2. The group III-N transistor of claim 1, wherein the second group III-N material is to provide a back barrier with a heterojunction formed along a first surface of the nanowire, and to induce a 2DEG within the channel region with a heterojunction along a second surface of the nanowire.
3. The group III-N transistor of claim 1, wherein the first surface is along a top surface of the nanowire, opposite the substrate, and wherein the second surface is along a bottom surface sidewall, opposite the top surface.
4. The group III-N transistor of claim 1, wherein the nanowire is disposed within a vertical stack of nanowires, wherein each of nanowires has a channel region consisting essentially of the first group III-N material, and wherein at least two of the plurality of nanowires are physically coupled together at a point along the longitudinal length by a third crystalline semiconductor material different than the first group III-N material.
5. The group III-N transistor of claim 4, wherein the third semiconductor has a larger bandgap than that of the first group III-N material.
6. The group III-N transistor of claim 5, wherein the first and third semiconductor materials comprise an epitaxial stack, wherein the nanowires each have a longitudinal axis extending parallel to the substrate.
7. The group III-N transistor of claim 1, wherein the drain region is separated from the channel region by an extrinsic drain region comprising a third group III-N material having a wider bandgap than that of the first group III-N material.
8. The high voltage transistor of claim 7, wherein the extrinsic drain region is an alloy of the first and third group III-N materials with a bandgap intermediate between those of the first and third group III-N materials.
9. The group III-N transistor of claim 1, further comprising:
a drain contact coaxially wrapping completely around the drain region; and
a source contact coaxially wrapping completely around the source region.
10. The group III-N transistor of claim 1, wherein the first group III-N material consists essentially of GaN, or consists essentially of InN, or consists essentially of Al xIn 1-xN, where x is less than 1, or consists essentially of Al xGa 1-xN, where x is less than 1.
11. The group III-N transistor of claim 10, wherein the second group III-N comprises AlN, GaN, Al yIn 1-yN, or Al yGa 1-xN, where y is greater than x.
12. The group III-N transistor of claim 11, wherein the third group III-N comprises AlN, GaN, InN, Al zIn 1-zN, or Al zGa 1-zN, where z is different than x.
13. The group III-N transistor of claim 12, wherein the drain region consists essentially of the first group III-N material.
14. A system on chip (SoC), comprising:
a power management integrated circuit (PMIC) including at least one of a switching voltage regulator or switching mode DC-DC converter; and
an RF integrated circuit (RFIC) including a power amplifier operable to operate with a cut-off frequency, F t and maximum oscillation frequency, F max of both at least 20 GHz, and generate a carrier wave frequency of at least 2 GHz, wherein both of the PMIC and RFIC are monolithically integrated onto a same substrate, and wherein at least one of PMIC and RFIC include the high voltage transistor of claim 1.
15. The SoC of claim 14, further comprising:
a controller of at least one of the PMIC and RFIC integrated onto the substrate, wherein the controller comprises CMOS technology fabricated with silicon field effect transistors.
16. A mobile computing device, comprising:
a touchscreen;
a battery;
an antenna; and
the SoC of claim 14, wherein the PMIC is coupled to the battery and wherein the RFIC is coupled to the antenna.
17. The mobile computing device of claim 16, further comprises a first and second processor core, each core operably coupled to the touchscreen, the PMIC and RFIC, wherein the first and second processor cores comprise CMOS technology fabricated with silicon field effect transistors.