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1. (WO2005104225) METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A NOTCHED CONTROL ELECTRODE AND STRUCTURE THEREOF
국제사무국에 기록된 최신 서지정보   

공개번호:    WO/2005/104225    국제출원번호:    PCT/US2005/002133
공개일: 03.11.2005 국제출원일: 21.01.2005
IPC:
H01L 21/4763 (2006.01), H01L 29/76 (2006.01)
출원인: FREESCALE SEMICONDUCTOR, INC. [US/US]; 6501 William Cannon Drive West, Austin, Texas 78735 (US) (For All Designated States Except US).
ORLOWSKI, Marius K. [DE/US]; (US) (For US Only).
BURNETT, James D. [US/US]; (US) (For US Only)
발명자: ORLOWSKI, Marius K.; (US).
BURNETT, James D.; (US)
대리인: KING, Robert L.; 7700 W. Parmer Lane, MD: TX32/PL02, Austin, Texas 78729 (US)
우선권 정보:
10/811,461 26.03.2004 US
발명의 명칭: (EN) METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A NOTCHED CONTROL ELECTRODE AND STRUCTURE THEREOF
(FR) PROCEDE PERMETTANT DE FORMER UN DISPOSITIF A SEMI-CONDUCTEUR DOTE D'UNE ELECTRODE DE COMMANDE A ENCOCHE ET SA STRUCTURE
요약서: front page image
(EN)A method for forming a semiconductor device (10) includes providing a substrate (20) having a surface; forming an insulating layer (22) over the surface of the substrate (20); forming a first patterned conductive layer (30) over the insulating layer (22); forming a second patterned conductive layer (32) over the first patterned conductive layer (30); forming a patterned non-insulating layer (34) over the second patterned conductive layer (32); and selectively removing portions of the first and second patterned conductive layers (30, 32) to form a notched control electrode for the semiconductor device (10).
(FR)L'invention concerne un procédé permettant de former un dispositif à semi-conducteur (10) qui consiste à fournir un substrat (20) doté d'une surface; à former une couche d'isolation (22) sur la surface dudit substrat (20); à former une première couche conductrice (30) à motifs sur la couche d'isolation (22); à former une seconde couche conductrice (32) à motifs sur la première couche conductrice (30) à motifs; à former une couche à motifs (34) non isolante sur la seconde couche conductrice (32) à motifs; et à retirer sélectivement des parties des première et secondes couches conductrices (30, 32) à motifs afin de former une électrode de commande à encoche destinée au dispositif à semi-conducteur (10).
지정국: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
공개언어: English (EN)
출원언어: English (EN)