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1. WO2022075003 - 半導体装置

第三者情報を提供
パーマリンク
公開番号 WO/2022/075003
公開日 14.04.2022
国際出願番号 PCT/JP2021/033155
国際出願日 09.09.2021
IPC
H01L 25/07 2006.1
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
25複数の個々の半導体または他の固体装置からなる組立体
03すべての装置がグループH01L27/00~H01L51/00の同じサブグループに分類される型からなるもの,例.整流ダイオードの組立体
04個別の容器を持たない装置
07装置がグループH01L29/00に分類された型からなるもの
CPC
H01L 2224/0603
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
0601Structure
0603Bonding areas having different sizes, e.g. different heights or widths
H01L 2224/06181
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
061Disposition
0618being disposed on at least two different sides of the body, e.g. dual array
06181On opposite sides of the body
H01L 2224/40225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
39Structure, shape, material or disposition of the strap connectors after the connecting process
40of an individual strap connector
401Disposition
40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
40221the body and the item being stacked
40225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 25/07
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; ; Multistep manufacturing processes thereof
03all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
04the devices not having separate containers
07the devices being of a type provided for in group H01L29/00
H01L 2924/19107
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
191Disposition
19101of discrete passive components
19107off-chip wires
出願人
  • ローム株式会社 ROHM CO., LTD. [JP]/[JP]
発明者
  • 林口　匡司 HAYASHIGUCHI Masashi
  • 小野寺　健一 ONODERA Kenichi
代理人
  • 臼井　尚 USUI Takashi
  • 鈴木　泰光 SUZUKI Yasumitsu
優先権情報
2020-16928506.10.2020JP
公開言語 (言語コード) 日本語 (ja)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
front page image
要約
(EN) This semiconductor device comprises: a plurality of semiconductor elements connected in parallel to each other; a rectification element connected in anti-parallel to the plurality of semiconductor elements; a power terminal electrically connected to the plurality of semiconductor elements; and a conductor that includes a pad part to which the plurality of semiconductor elements are joined and which is electrically connected to the power terminal and the plurality of semiconductor elements. The plurality of semiconductor elements include a first element and a second element. The shortest conduction path to the power terminal of the first element is shorter than the shortest conduction path to the power terminal of the second element. The pad part includes a first portion to which the first element is joined and a second portion to which the second element is joined. The rectification element is disposed in the first portion of the pad part.
(FR) Dispositif à semi-conducteur comprenant : une pluralité d'éléments semi-conducteurs connectés en parallèle les uns aux autres ; un élément de redressement connecté en antiparallèle à la pluralité d'éléments semi-conducteurs ; une borne d'alimentation électriquement connectée à la pluralité d'éléments semi-conducteurs ; et un conducteur qui comprend une partie plot à laquelle la pluralité d'éléments semi-conducteurs sont connectés et qui est électriquement connecté à la borne électrique et à la pluralité d'éléments semi-conducteurs. La pluralité d'éléments semi-conducteurs comprend un premier élément et un second élément. Le trajet de conduction le plus court jusqu'à la borne d'alimentation du premier élément est plus court que le trajet de conduction le plus court jusqu'à la borne d'alimentation du second élément. La partie plot comprend une première portion à laquelle le premier élément est relié et une seconde portion à laquelle le second élément est relié. L'élément de redressement est disposé dans la première portion de la partie plot.
(JA) 半導体装置は、互いに並列接続された複数の半導体素子と、前記複数の半導体素子に逆並列に接続された整流素子と、前記複数の半導体素子に導通する電力端子と、前記複数の半導体素子が接合されたパッド部を含み且つ前記電力端子および前記複数の半導体素子に導通する導電体と、を備える。前記複数の半導体素子は、第１素子および第２素子を含む。前記第１素子の前記電力端子までの最短導通経路は、前記第２素子の前記電力端子までの最短導通経路よりも短い。前記パッド部は、前記第１素子が接合された第１部と、前記第２素子が接合された第２部とを含む。前記整流素子は、前記パッド部の前記第１部に配置されている。
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