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1. WO2019198199 - 半導体装置

公開番号 WO/2019/198199
公開日 17.10.2019
国際出願番号 PCT/JP2018/015385
国際出願日 12.04.2018
IPC
H01L 23/12 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
12マウント,例.分離できない絶縁基板
H01L 23/29 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
28封緘,例.封緘層,被覆
29材料に特徴のあるもの
CPC
H01L 2224/48137
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
48137the bodies being arranged next to each other, e.g. on a common substrate
H01L 2224/49175
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
49of a plurality of wire connectors
491Disposition
4912Layout
49175Parallel arrangements
H01L 2224/73265
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73251on different surfaces
73265Layer and wire connectors
H01L 23/12
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
H01L 23/29
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
29characterised by the material ; , e.g. carbon
H01L 2924/181
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
15Details of package parts other than the semiconductor or other solid state devices to be connected
181Encapsulation
出願人
  • 三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP]/[JP]
発明者
  • 宮脇 勝巳 MIYAWAKI Katsumi
代理人
  • 大岩 増雄 OIWA Masuo
  • 村上 啓吾 MURAKAMI Keigo
  • 竹中 岑生 TAKENAKA Mineo
  • 吉澤 憲治 YOSHIZAWA Kenji
優先権情報
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
要約
(EN)
This semiconductor device (50) is provided with: a lead frame (1) having a lead (23) and a die pad (24); a printed board (3) provided with electrodes (25, 26) which connect the lead (23) and the die pad (24), respectively, a wiring pattern (11), and an opening (22) which exposes a portion of the surface of the die pad (1); a semiconductor element (5) which is mounted on the surface of a metal block (15) bonded to the surface of the die pad (24), which is exposed by the opening (22), and processes a high-frequency signal connected to the wiring pattern (11) by a metal wire (6); an electronic component (4) which is connected to the wiring pattern (11) and mounted on the surface of the printed board (3); and a sealing resin (2) which seals the printed board (3), the semiconductor element (5), the electronic component (4), and the metal wire (6) such that rear surfaces of the lead (23) and the die pad (24) are exposed.
(FR)
L'invention concerne un dispositif à semi-conducteur (50) comprenant : une grille de connexion (1) ayant un fil (23) et une plage de connexion (24) ; une carte imprimée (3) comprenant des électrodes (25, 26) qui connectent le fil (23) et la plage de connexion (24), respectivement, un motif de câblage (11), et une ouverture (22) qui expose une partie de la surface de la plage de connexion (1) ; un élément semi-conducteur (5) qui est monté sur la surface d'un bloc métallique (15) liée à la surface de la plage de connexion (24), qui est exposée par l'ouverture (22), et traite un signal haute fréquence connecté au motif de câblage (11) par un fil métallique (6) ; un composant électronique (4) qui est connecté au motif de câblage (11) et monté sur la surface de la carte imprimée (3) ; et une résine d'étanchéité (2) qui scelle la carte imprimée (3), l'élément semi-conducteur (5), le composant électronique (4) et le fil métallique (6) de telle sorte que des surfaces arrière du fil (23) et de la plage de connexion (24) sont exposées.
(JA)
半導体装置(50)は、リード(23)及びダイパッド(24)を有するリードフレーム(1)と、リード(23)及びダイパッド(24)のそれぞれを接続する電極(25、26)、配線パターン(11)、ダイパッド(1)の表面の一部を露出する開口(22)、を備えたプリント基板(3)と、開口(22)により露出されたダイパッド(24)の表面に接合された金属ブロック(15)の表面に実装され、配線パターン(11)に金属ワイヤ(6)で接続された高周波信号を処理する半導体素子(5)と、配線パターン(11)に接続されると共にプリント基板(3)の表面に実装された電子部品(4)と、リード(23)及びダイパッド(24)における裏面が露出するように、プリント基板(3)、半導体素子(5)、電子部品(4)、金属ワイヤ(6)を封止する封止樹脂(2)と、を備えている。
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