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1. (WO2019042036) THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF
Document

Description

Title of Invention 0001   0002   0003   0004   0005   0006   0007   0008   0009   0010   0011   0012   0013   0014   0015   0016   0017   0018   0019   0020   0021   0022   0023   0024   0025   0026   0027   0028   0029   0030   0031   0032   0033   0034   0035   0036   0037   0038   0039   0040   0041   0042   0043   0044   0045   0046   0047   0048   0049   0050   0051   0052   0053   0054   0055   0056   0057   0058   0059   0060   0061   0062   0063   0064   0065   0066   0067   0068   0069   0070   0071   0072   0073   0074   0075   0076   0077   0078   0079   0080   0081   0082   0083   0084   0085   0086   0087   0088   0089   0090   0091   0092   0093   0094   0095   0096   0097   0098   0099   0100   0101   0102   0103   0104   0105   0106   0107   0108   0109   0110   0111   0112   0113   0114   0115   0116   0117   0118   0119   0120   0121   0122  

Claims

1   2   3   4   5   6   7   8   9   10   11   12   13   14   15   16   17   18   19   20  

Drawings

1A   1B   1C   1D   1E   1F   2A   2B   3   4A   4B   4C   4D   4E   4F   4G   4H  

Description

Title of Invention : THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

[0001]
CROSS-REFERENCE TO RELATED APPLICATIONS
[0002]
This application claims priority to Chinese Patent Application No. 201710770822.1, filed on August 31, 2017, which is incorporated herein by reference in their entireties.

TECHNICAL FIELD

[0003]
The present disclosure generally relates to the field of semiconductor technology, and more particularly, to a three-dimensional (3D) memory device and a fabricating method thereof.

BACKGROUND

[0004]
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.
[0005]
As semiconductor technology advances, 3D memory devices, such as 3D NAND memory devices, keep scaling more oxide/nitride (ON) layers to improve the area utilization of wafers. The staircase structure in the 3D NAND memory device is also referred to as a gate stack, which needs to be connected to an external circuit through multiple metal lines for implementing a memory function. Since the number of steps in the staircase structure keeps increasing, it is a challenge to control the size of the steps in the staircase structure during the existing fabricating processes, which may cause many problems, such as the leakage problem of the connection between the metal lines and the gate stack, the breakdown problem of the gate stack, etc.
[0006]
BRIEF SUMMARY
[0007]
Embodiments of a method for forming a three-dimensional (3D) memory devices are disclosed herein. The method comprises: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.
[0008]
The method further comprises: before forming the first insulating layer, forming a metal-oxide-semiconductor field-effect transistor on the substrate in the peripheral region; wherein forming the first insulating layer includes forming the first insulating layer to cover the metal-oxide-semiconductor field-effect transistor.
[0009]
In some embodiments, forming the first insulating layer comprises: forming the first insulating layer on the substrate in both the peripheral region and the core region; and removing a portion of the first insulating layer in the core region, such that the remaining portion of the first insulating layer in the peripheral region has the slope near the boundary between the peripheral region and the core region.
[0010]
In some embodiments, forming the first insulating layer comprises: forming the first insulating layer having a slope with a slant angle in a range from about 30 degrees to about 90 degrees.
[0011]
In some embodiments, forming the alternating conductive/dielectric stack comprises: forming an alternating dielectric stack on the substrate and the first insulating layer, the alternating dielectric stack including a first lateral portion on the substrate in the core region, a second lateral portion on a top surface of the first insulating layer in the peripheral region, and an inclined portion on the slope of the first insulating layer near the boundary between the peripheral region and the core region; removing the second lateral portion of the alternating dielectric stack; planarizing a top surface of the inclined portion of the alternating dielectric stack, such that the top surfaces of the first insulating layer, the inclined portion of the alternating dielectric stack, and the first lateral portion of the alternating dielectric stack are co-planar; and converting remaining portions of the alternating dielectric stack to the alternating conductive/dielectric stack.
[0012]
In some embodiments, forming the alternating dielectric stack comprises: forming at least 32 dielectric layer pairs stacked in a vertical direction above the substrate, each dielectric layer pair including a first dielectric layer and a second dielectric layer that has a material different with the first dielectric layer.
[0013]
In some embodiments, forming the alternating dielectric stack comprises: forming at least 32 dielectric layer pairs stacked in the vertical direction, each dielectric layer pair including a silicon oxide layer and a silicon nitride layer.
[0014]
In some embodiments, forming the alternating dielectric stack comprises: forming a bottom second dielectric layer on a top surface of the first insulating layer as a first chemical mechanical polishing stop layer in the peripheral region; and forming a top second dielectric layer as a second chemical mechanical polishing stop layer in the core region; wherein the first chemical mechanical polishing stop layer and the second chemical mechanical polishing stop layer are approximately co-planar.
[0015]
In some embodiments, removing the second lateral portion of the alternating dielectric stack comprises: removing the first dielectric layers and the second dielectric layers of the alternating dielectric stack in the alternating dielectric stack except the bottom second dielectric layer.
[0016]
In some embodiments, planarizing the top surface of the inclined portion of the alternating dielectric stack comprises: removing an upper portion of the inclined portion of the alternating dielectric stack that is higher than a top surface of the first chemical mechanical polishing layer or the second chemical mechanical polishing stop layer.
[0017]
In some embodiments, converting remaining portions of the alternating dielectric stack to the alternating conductive/dielectric stack comprises: replacing the second dielectric layers in the alternating dielectric stack with conductive layers.
[0018]
In some embodiments, forming the plurality of contacts comprises: forming a second insulating layer in both the peripheral region and the core region to cover a top surface of the alternating conductive/dielectric stack; and forming a plurality of contacts in the second insulating layer to electrically contact with the plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack; wherein the plurality of contacts have a same height.
[0019]
In some embodiments, forming the plurality of contacts comprises: forming a plurality of through holes in the second insulating layer in a single etching process; and depositing a conductive material into the plurality of through holes to form the plurality of contacts.
[0020]
In some embodiments, the method further comprises: forming two contacts in the first and second insulating layers to electrically contact a source electrode and a drain electrode of the metal-oxide-semiconductor field-effect transistor respectively.
[0021]
Another aspect of the present disclosure provides a three-dimensional (3D) memory device, comprising: an insulating layer on a substrate in a peripheral region, the insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; an alternating conductive/dielectric stack on the substrate and the slope of the insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the insulating layer; and a plurality of contacts in electrical contact with a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.
[0022]
The device further comprises: a metal-oxide-semiconductor field-effect transistor on the substrate in the peripheral region, wherein the insulating layer covers the metal-oxide-semiconductor field-effect transistor; and two contacts in the insulating layer and in electrical contact with a source electrode and a drain electrode of the metal-oxide-semiconductor field-effect transistor respectively.
[0023]
In some embodiments, a slant angle of the slope of the insulating layer is in a range from about 30 degrees to about 90 degrees.
[0024]
In some embodiments, the alternating conductive/dielectric stack comprises: at least 32 conductive/dielectric layer pairs, each including a dielectric layer and a conductive layer.
[0025]
In some embodiments, a top surface of the lateral portion of the alternating conductive/dielectric stack is co-planar with a top surface of the inclined portion of the alternating conductive/dielectric stack.
[0026]
In some embodiments, the plurality of contacts have a same height and are formed in a same process.
[0027]
Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.
[0029]
FIGs. 1A-1F illustrate cross-sectional views of an exemplary 3D memory device at certain fabricating stages of a fabricating method;
[0030]
FIG. 2A illustrates a cross-sectional view of an electronic scan diagram of a staircase region of a 3D memory device including a misalignment between a contact and a step;
[0031]
FIG. 2B illustrates a cross-sectional view of an electronic scan diagram of a step perforation in a 3D memory device;
[0032]
FIG. 3 illustrates a flow diagram of an exemplary method for forming a 3D memory device in accordance with some embodiments of the present disclosure; and
[0033]
FIGs. 4A-4H illustrate cross-sectional views of an exemplary 3D memory device at certain fabricating stages of the method shown in FIG. 3.
[0034]
Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0035]
Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.
[0036]
It is noted that references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some embodiments, ” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
[0037]
In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.
[0038]
It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something) .
[0039]
Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
[0040]
As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.
[0041]
As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnection layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
[0042]
As used herein, the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30%of the value (e.g., ±10%, ±20%, or ±30%of the value) .
[0043]
As used herein, the term “3D memory device” refers to a semiconductor device with vertically-oriented strings of memory cell transistors (i.e., region herein as “memory strings, ” such as NAND strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to a lateral surface of a substrate.
[0044]
FIGs. 1A-1F illustrate cross-sectional views of an exemplary 3D memory device at certain fabricating stages of a fabricating method. The fabricating method includes the following operations.
[0045]
As shown in FIG. 1A, a substrate 100 can be provided. In some embodiments, substrate 100 can be any suitable semiconductor substrate having any suitable structure, such as a monocrystalline single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multi-layer substrate, etc.
[0046]
In some embodiments, substrate 100 can be divided into a peripheral region 110 and a core region 120. Peripheral region 110 can be on the side of core region 120. As shown in FIG. 1A, in some embodiments, a metal-oxide-semiconductor field-effect transistor (MOSFET) 112 can be formed on substrate 100 in peripheral region 110.
[0047]
As shown in FIG. 1B, an insulating layer 114 can be formed on substrate 100 in peripheral region 110 to cover MOSFET 112. In some embodiments, insulating layer 114 can include any suitable insulating material and/or dielectric material, such as silicon oxide, etc. In some embodiments, an oxide layer can be deposited on substrate 100 to cover MOSFET 112. A portion of the oxide layer in core region 120 can be etched and removed. The remaining portion of the oxide layer in peripheral region 110 forms insulating layer 114. In some embodiments, insulating layer 114 at the boundary of peripheral region 110 that is adjacent to core region 120 can have a slope.
[0048]
As shown in FIG. 1C, an alternating dielectric stack 200 including a plurality of dielectric layer pairs can be formed on substrate 100 and insulating layer 114. Alternating dielectric stack 200 can include an alternating stack of a first dielectric layer 202 (e.g., of silicon oxide) and a second dielectric layer 204 (e.g., of silicon nitride) that is different from first dielectric layer. In core region 120, the plurality of first dielectric layers 202 and second dielectric layers 204 are extended in a lateral direction that is parallel to the surface of substrate 100. In peripheral region 110, the plurality of first dielectric layers 202 and second dielectric layers 204 can be extended along the surface of insulating layer 114. That is, at the boundary of peripheral region 110 and core region 120, the plurality of first dielectric layers 202 and second dielectric layers 204 can be inclined and extended along a direction that is parallel to the top surface of the slope of insulating layer 114.
[0049]
In some embodiments, there are more layers than the dielectric layer pairs made of different materials and with different thicknesses in alternating dielectric stack 200. For example, a bottom layer and a top layer of alternating dielectric stack 200 can be first dielectric layers that have a thickness larger than the thicknesses of other interlayers. Alternating dielectric stack 200 can be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD) , Physical Vapor Deposition (PVD) , Atomic Layer Deposition (ALD) , or any combination thereof.
[0050]
In some embodiments, alternating dielectric stack 200 can include a plurality of oxide/nitride layer pairs. Each dielectric layer pair includes a layer of silicon oxide 202 and a layer of silicon nitride 204. The plurality of oxide/nitride layer pairs are also referred to herein as an “alternating oxide/nitride stack. ” That is, in alternating dielectric stack 200, multiple oxide layers 202 and multiple nitride layers 204 alternate in a vertical direction. In other words, except a top and a bottom layer of a given alternating oxide/nitride stack, each of the other oxide layers 202 can be sandwiched by two adjacent nitride layers 204, and each of nitride layers 204 can be sandwiched by two adjacent oxide layers 202.
[0051]
Oxide layers 202 can each have the same thickness or have different thicknesses. For example, a thickness of each oxide layer 202 can be in a range from 10nm to 100nm, preferably about 30nm. Similarly, nitride layers 204 can each have the same thickness or have different thicknesses. For example, a thickness of each nitride layer 204 can be in a range from 10nm to 100nm, preferably about 35nm.
[0052]
It is noted that, in the present disclosure, oxide layers 202 and/or nitride layers 204 can include any suitable oxide materials and/or nitride materials. For example, the oxide materials can include silicides, and the element of nitride materials can include, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , doped silicon, silicides, or any combination thereof. In some embodiments, oxide layers 202 can be silicon oxide layers, and nitride layers 204 can be silicon nitride layer.
[0053]
Alternating dielectric stack 200 can include any suitable number of layers of oxide layers 202 and nitride layers 204. In some embodiments, a total number of layers of oxide layers 202 and nitride layers 204 in alternating dielectric stack 200 is equal to or larger than 64. That is, a number of oxide/nitride layer pairs can be equal to or larger than 32. In some embodiments, alternating oxide/nitride stack 200 includes more oxide layers or more nitride layers with different materials and/or thicknesses than the oxide/nitride layer pair.
[0054]
As shown in FIG. 1D, portions of alternating dielectric stack 200 can be removed to form a staircase structure 300 at the edge of alternating dielectric stack 200 in core region 120. In some embodiments, alternating dielectric stack 200 in peripheral region 110 can be removed. Multiple etch-trim processes can be performed repeatedly to form a set of steps. In some embodiments, each step can include a dielectric layer pair. As such, each step can expose a portion of the top surface of one second dielectric layer 204.
[0055]
In some embodiments, the etch-trim processes can include a set of repeating etch-trim processes to form staircase structure 300 including a set of steps at the edge alternating dielectric stack 200.
[0056]
Specifically, for forming each step, a photoresist layer (not shown) can be used as a mask to expose a portion of the top surface of alternating dielectric stack 200. For forming the first step, a width of the exposed top surface of alternating dielectric stack 200 can be a step width. In some embodiments, an anisotropic etching process, such as a reactive ion etching (RIE) process, or other suitable dry/wet etching process, can be performed to remove the exposed layer (e.g., second dielectric layer 204) that is exposed through the mask (i.e., the photoresist layer) . The etching process can stop on the next lower layer (e.g.., first dielectric layer 202) . The pattern in the mask (i.e., the photoresist layer) is then transferred to the layer (e.g., second dielectric layer 204) that has been etched. The exposed next lower layers (e.g., first dielectric layers 202) can be then removed by another etching process that stops on the next lower layers (e.g., second dielectric layer 204) . As such, the first step can be created on the first two top layers of alternating dielectric stack 200.
[0057]
Next, the mask (i.e., the photoresist layer) can be reduced in size by removing a portion of the mask (also known as “trimming” ) above alternating dielectric stack 200, such as by an isotropic etching process, to expose another step width of alternating dielectric stack 200. The method can proceed by subjecting the structure to two anisotropic etching processes, including removing exposed portions of the two exposed layers (e.g., two second dielectric layers 204) , and subsequently removing exposed portions of the two exposed next lower layers (e.g., first dielectric layers 202) . As such, the first step can be lowered to the third and fourth top layers of alternating dielectric stack 200, and a second step can be created on the first two top layers of alternating dielectric stack 200.
[0058]
In some embodiments, the successive reduction in size of the mask (i.e., photoresist layer 130) and the two-step etching processes (also referred as etch-trim processes) can be repeated such that staircase structure 300 including a set of steps can be formed on the edge of alternating dielectric stack 200 in core region 120, as shown in FIG. 1D. The photoresist layer can be then removed. In some embodiments, the removal process can include any suitable etching processes and cleaning processes.
[0059]
As shown in FIG. 1E, a height of insulating layer 114 can be increased to cover staircase structure 300. In some embodiments, a deposition process can be performed to increase the height of insulating layer 114 in core region 120, such that insulating layer 114 can cover alternating dielectric stack 200 including staircase structure 300. A chemical mechanical polishing (CMP) process can be performed to planarize the top surface of insulating layer 114.
[0060]
As shown in FIG. 1F, second dielectric layers 204 in alternating dielectric stack 200 can be replaced by conductive layers 206, such that alternating dielectric stack 200 is converted to an alternating conductive/dielectric stack 220. Conductive layers 206 can be used as multiple word lines. Multiple contacts 310 penetrating insulating layer 114 can be formed to electrically contact with conductive layers 206 respectively through staircase structure 300. As such, the multiple word lines can be connected to a wiring layer through multiple contacts 310.
[0061]
In some embodiments, a gate replacement process (also known as the “word line replacement” process) can be performed to replace second dielectric layers 204 (e.g., silicon nitride) of alternating dielectric stack 200 with conductive layers 206 (e.g., W) . As a result, after the gate replacement process, alternating dielectric stack 200 can become an alternating conductive/dielectric stack 220. The replacement of second dielectric layers 204 with conductive layers 206 can be performed by wet etching second dielectric layers 204 (e.g., silicon nitride) selective to first dielectric layers 202 (e.g., silicon oxide) and filling the structure with conductive layers 206 (e.g., W) . Conductive layers 206 can be filled by PVD, CVD, ALD, any other suitable process, or any combination thereof. Conductive layers 206 can include any suitable conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof.
[0062]
In some embodiments, multiple contacts 310 can be formed through insulating layer 114 by first etching multiple vertical through holes (e.g., by wet etching and/or dry etching) , followed by filling the through holes with conductive materials using ALD, CVD, PVD, any other suitable processes, or any combination thereof. The conductor materials used to fill the through holes can include, but are not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof. It is understood that the process for forming multiple contacts 310 can include multiple processes, for example, photolithography, etching, thin film deposition, and CMP, etc.
[0063]
In some embodiments, the above method for forming the 3D memory device may have some drawbacks. In one aspect, as the number of the layers in alternating conductive/dielectric stack 220 keeping increases, multiple trim-etch processes are required to be performed. Thus, the cost of the multiple photoresist layers and multiple etching processes to form the staircase structure can be higher and higher. For example, to form a 39 levels of staircases, at least 9 photoresist layers are required to be used as the masks.
[0064]
In another aspect, due to the difficulty in controlling the step size, the step size deviation can cause position deviation of the contact hole in the subsequent etching process. FIG. 2A illustrates a cross-sectional view of an electronic scan diagram of a staircase region of a 3D memory device including a misalignment between a contact and a step. As shown, the misalignment between contact 310 and the step in the dashed box is caused by the step size deviation. Since two contacts 310 are connected to a same step, a gate short problem can be caused and resulting in a word line leakage problem.
[0065]
In another aspect, due to the difficulty in controlling the etching depth, the step depth deviation can cause over-etching problem in forming the contact holes. FIG. 2B illustrates a cross-sectional view of an electronic scan diagram of a step perforation in a 3D memory device. As shown in the dashed circular region, a contact 310 penetrates conductive layer 206 due to the over-etching of the contact hole. The step perforation can cause leakage problem or breakdown problem.
[0066]
Accordingly, various embodiments in accordance with the present disclosure provide a method for forming a 3D memory device. In the disclosed method, an alternating conductive/dielectric stack can include an inclined portion formed on a slope of an insulating layer. The inclined portion of the alternating conductive/dielectric stack can be used to replace the staircase structure. The contacting surfaces of the multiple conductive layers of the alternating conductive/dielectric stack can be at the inclined portion and co-planar with each other. Thus, multiple contacts can be formed in a single process to electronically contact with the multiple conductive layers. Without forming the staircase structure, multiple trim-etch processes are not necessary, the cost of multiple photoresist masks and etching processes can be saved. Moreover, the drawbacks including short problem, leakage problem and breakdown problem caused by the difficulty of controlling the staircase structure fabricating process can be avoided.
[0067]
FIG. 3 illustrates a flow diagram of an exemplary method for forming a 3D memory device in accordance with some embodiments of the present disclosure. FIGs. 4A-4H illustrate cross-sectional views of an exemplary 3D memory device at certain fabricating stages of the method shown in FIG. 3.
[0068]
As shown in FIG. 3, the method can start at operation S310, in which a substrate including a peripheral region and a core region can be provided. A MOSFET can be formed on the substrate in the peripheral region. An insulating layer can be formed on the substrate in the peripheral region to cover the MOSFET.
[0069]
As shown in FIG. 4A, a substrate 100 can be provided. In some embodiments, substrate 100 can be any suitable semiconductor substrate having any suitable structure, such as a monocrystalline single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multi-layer substrate, etc.
[0070]
In some embodiments, substrate 100 can be divided into a peripheral region 110 and a core region 120. Peripheral region 110 can surround core region 120. As shown in FIG. 1A, in some embodiments, a metal-oxide-semiconductor field-effect transistor (MOSFET) 112 can be formed on substrate 100 in peripheral region 110.
[0071]
In some embodiments, an insulating layer 114 can be formed on substrate 100 in peripheral region 110 to cover MOSFET 112. Insulating layer 114 can include any suitable insulating material and/or dielectric material, such as silicon oxide, etc. In some embodiments, an oxide layer can be deposited on substrate 100 to cover MOSFET 112, as shown in FIG. 4A. A portion of the oxide layer in core region 120 can be etched and removed. For example, a hard mask etching process can be used to etch and remove the oxide layer in the core region. The remaining portion of the oxide layer in peripheral region 110 forms insulating layer 114, as shown in FIG. 4B.
[0072]
In some embodiments, a thickness of peripheral region 110 in peripheral region 110 can be approximately equal to a thickness of an alternating dielectric stack formed in a subsequent process. Insulating layer 114 at the boundary of peripheral region 110 that is adjacent to core region 120 can have a slope, as shown in FIG. 4B. A slant angle of the slope α can be in a range between about 30 degrees and about 90 degrees, preferably equal to about 60 degrees. In some embodiments, within the size limitation of the peripheral region 110, the slant angle α of the slope can be as larger as possible.
[0073]
It should be noted that, in the subsequent fabricating processes for forming the three-dimensional memory device, an inclined alternating layer stack can be formed on the slope of insulating layer 114 to replace the staircase structure described above in connection with FIGs. 1D-1F. The conductive layers in the inclined alternating layer stack can be used to connect to contacts. Thus, a larger slant angle of the slope α can ensure a larger distance between adjacent conductive layers in the inclined alternating layer stack, and a larger thickness of the conductive layers in the inclined alternating layer stack. Thus, the contacts can be easily formed to be in contact with corresponding conductive layers, thereby ensuring an electrical safety of the alternating layer stack.
[0074]
Referring back to FIG. 3, the method can proceed to operation S320, in which an alternating dielectric stack including a plurality of dielectric layer pairs can be formed on the substrate and the insulating layer.
[0075]
As shown in FIG. 4C, alternating dielectric stack 200 including a plurality of dielectric layer pairs can be formed on substrate 100 and insulating layer 114. Alternating dielectric stack 200 can include an alternating stack of a first dielectric layer 202 (e.g., of silicon oxide) and a second dielectric layer 204 (e.g., of silicon nitride) that is different from first dielectric layer. In core region 120, the plurality of first dielectric layers 202 and second dielectric layers 204 are extended in a lateral direction that is parallel to the surface of substrate 100. In peripheral region 110, the plurality of first dielectric layers 202 and second dielectric layers 204 can be extended along the surface of insulating layer 114. That is, at the boundary of peripheral region 110 and core region 120, an inclined portion of the plurality of first dielectric layers 202 and second dielectric layers 204 can be inclined at the slant angle α and extended along a direction that is parallel to the top surface of the slope of insulating layer 114.
[0076]
In some embodiments, there are more layers than the dielectric layer pairs made of different materials and with different thicknesses in alternating dielectric stack 200. In some embodiments, a top layer of alternating dielectric stack 200 can be a second dielectric layer that has a thickness larger than the thicknesses of other interlayers. The top layer of alternating dielectric stack 200 can be used as a chemical mechanical polishing (CMP) stop layer 420 in core region 120. Similarly, a bottom layer of alternating dielectric stack 200 can be a second dielectric layer and can be used as a CMP stop layer 410 in peripheral region 110. CMP stop layer 410 in peripheral region 110 and CMP stop layer 420 in core region 120 can be approximately co-planar, as the level of the dashed line shown in FIG. 4C.
[0077]
In some embodiments, alternating dielectric stack 200 can be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD) , Physical Vapor Deposition (PVD) , Atomic Layer Deposition (ALD) , or any combination thereof.
[0078]
In some embodiments, alternating dielectric stack 200 can include a plurality of oxide/nitride layer pairs. Each dielectric layer pair includes a layer of silicon oxide 202 and a layer of silicon nitride 204. The plurality of oxide/nitride layer pairs are also referred to herein as an “alternating oxide/nitride stack. ” That is, in alternating dielectric stack 200, multiple oxide layers 202 and multiple nitride layers 204 alternate in a vertical direction. In other words, except a top and a bottom layer of a given alternating oxide/nitride stack, each of the other oxide layers 202 can be sandwiched by two adjacent nitride layers 204, and each of the other nitride layers 204 can be sandwiched by two adjacent oxide layers 202.
[0079]
Oxide layers 202 can each have the same thickness or have different thicknesses. For example, a thickness of each oxide layer 202 can be in a range from 10nm to 100nm, preferably about 30nm. Similarly, nitride layers 204 can each have the same thickness or have different thicknesses. For example, a thickness of each nitride layer 204 can be in a range from 10nm to 100nm, preferably about 35nm.
[0080]
It is noted that, in the present disclosure, oxide layers 202 and/or nitride layers 204 can include any suitable oxide materials and/or nitride materials. For example, the oxide materials can include silicides, and the element of nitride materials can include, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , doped silicon, silicides, or any combination thereof. In some embodiments, oxide layers 202 can be silicon oxide layers, and nitride layers 204 can be silicon nitride layer.
[0081]
Alternating dielectric stack 200 can include any suitable number of layers of oxide layers 202 and nitride layers 204. In some embodiments, a total number of layers of oxide layers 202 and nitride layers 204 in alternating dielectric stack 200 is equal to or larger than 64. That is, a number of oxide/nitride layer pairs can be equal to or larger than 32. In some embodiments, alternating oxide/nitride stack 200 includes more oxide layers or more nitride layers with different materials and/or thicknesses than the oxide/nitride layer pair.
[0082]
Referring back to FIG. 3, the method can proceed to operation S330, in which an upper portion of the alternating dielectric stack can be removed to expose the inclined portion of the alternating dielectric stack. In some embodiments, an upper portion of the alternating dielectric stack above CMP stop layer 410 can be removed by performing an etching back process, a chemical mechanical polishing (CMP) process, and a CMP stop layer removal process.
[0083]
As shown in FIG. 4D, a portion of alternating dielectric stack 200 in peripheral region 110 can be removed by performing an etching back process. For example, a hard mask layer can be formed to cover the portions of alternating dielectric stack 200 in core region 120 and on the slope of insulating layer 114. An etching back process can be performed to remove first dielectric layers 202 and second dielectric layers 204 in peripheral region 110 that are not covered by the hard mask layer. The etching back process can stop at CMP stop layer 410.
[0084]
As shown in FIG. 4E, a chemical mechanical polishing (CMP) process can be performed to remove the raised portion of alternating dielectric stack 200 above the level of CMP stop layer 410 and CMP stop layer 420. As such, second dielectric layers 204 in the inclined portion of alternating dielectric stack 200 can be exposed, and a top surface of the inclined portion of alternating dielectric stack 200 can be planarized and co-planar with CMP stop layer 410 and CMP stop layer 420.
[0085]
As shown in FIG. 4F, CMP stop layer 410 and CMP stop layer 420 can be then removed to expose the insulating layer in peripheral region 110 and top first dielectric layer 202 in core region 120. CMP stop layer 410 and CMP stop layer 420 can be removed by using any suitable process, such as a wet etching process. In some embodiments, when the thickness of alternating dielectric stack 200 in core region 120 is higher than the thickness of insulating layer 114 in peripheral region 110, some of the top layers of alternating dielectric stack 200 in core region 120 can also be removed.
[0086]
Referring back to FIG. 3, the method can proceed to operation S340, in which the second dielectric layers in the remaining portion of the alternating dielectric stack can be replaced with conductive layers, such that the remaining portion of the alternating dielectric stack is converted to an alternating conductive/dielectric stack.
[0087]
As shown in FIG. 4G, second dielectric layers 204 in alternating dielectric stack 200 can be replaced by conductive layers 206, such that alternating dielectric stack 200 is converted to an alternating conductive/dielectric stack 220. The alternating conductive/dielectric stack includes a lateral portion extended on the surface of substrate 100 in core region 120, and an inclined portion extended on the slope of insulating layer 114. Conductive layers 206 can be used as multiple word lines.
[0088]
Specifically, a gate replacement process (also known as the “word line replacement” process) can be performed to replace second dielectric layers 204 (e.g., silicon nitride) of alternating dielectric stack 200 with conductive layers 206 (e.g., W) . As a result, after the gate replacement process, alternating dielectric stack 200 can become an alternating conductive/dielectric stack 250. The replacement of second dielectric layers 204 with conductive layers 206 can be performed by wet etching second dielectric layers 204 (e.g., silicon nitride) selective to first dielectric layers 202 (e.g., silicon oxide) and filling the structure with conductive layers 206 (e.g., W) . Conductive layers 206 can be filled by PVD, CVD, ALD, any other suitable process, or any combination thereof. Conductive layers 206 can include any suitable conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof.
[0089]
Referring back to FIG. 3, the method can proceed to operation S350, in which multiple contacts can be formed to electronically contact with the conductive layers of the alternating conductive/dielectric stack respectively, and two contacts can be formed to electronically contact with the source and drain electrodes of the MOSFET respectively.
[0090]
As shown in FIG. 4H, a height of insulating layer 114 can be increased to cover the alternating conductive/dielectric stack 250. In some embodiments, a deposition process can be performed to increase the height of insulating layer 114 in peripheral region 110 and core region 120, such that insulating layer 114 can cover the top surface of the inclined portion and the lateral portion of the alternating conductive/dielectric stack 250. A chemical mechanical polishing (CMP) process can be performed to planarize the top surface of insulating layer 114.
[0091]
In some embodiments, multiple contacts 310 can be formed in insulating layer 114 to electrically contact with the inclined portions of multiple conductive layers 206 of the alternating conductive/dielectric stack 250 respectively. As such, the multiple word lines can be connected to a wiring layer through multiple contacts 310. Since the contacting surfaces of the inclined portions of multiple conductive layers 206 are co-planar, the lengths of multiple contacts 310 can equal to each other. That is, the inclined portions of the alternating conductive/dielectric stack 250 can be used to replace the staircase structure as shown in FIG. 1F.
[0092]
In some embodiments, multiple contacts 310 can be formed through insulating layer 114 by first etching multiple vertical through holes (e.g., by wet etching and/or dry etching) , followed by filling the through holes with conductive materials using ALD, CVD, PVD, any other suitable processes, or any combination thereof. The conductor materials used to fill the through holes can include, but are not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof. It is understood that the process for forming multiple contacts 310 can include multiple processes, for example, photolithography, etching, thin film deposition, and CMP, etc.
[0093]
As described above, since the contacting surfaces of the inclined portions of multiple conductive layers 206 are co-planar, the multiple vertical through holes can have a same depth. Therefore, the multiple vertical through holes can be formed by using a single etching process. Comparing to performing multiple etching processes to form multiple vertical through holes having different depths for the staircase structure, the above fabricating method has a simple process and has an improved efficiency.
[0094]
In some embodiments, two contacts 320 can be formed in insulating layer 114 to electrically contact with source electrode 116 and drain electrode 118 of MOSFET 112 respectively.
[0095]
Another aspect of the present disclosure provides a 3D memory device formed by using the disclosed method described above in connection with FIGs. 3 and 4A-4H. The 3D memory device can include an insulating layer on a substrate in a peripheral region. The insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate. The 3D memory device can further include an alternating conductive/dielectric stack on the substrate and the slope of the insulating layer. A lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the insulating layer. A top surface of the lateral portion of the alternating conductive/dielectric stack is co-planar with a top surface of the inclined portion of the alternating conductive/dielectric stack.
[0096]
The 3D memory device can further include a plurality of contacts in electrically contact with a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack. The plurality of contacts can have a same height and are formed in a same process.
[0097]
In some embodiments, the 3D memory device can further include a metal-oxide-semiconductor field-effect transistor on the substrate in the peripheral region that is covered by the insulating. Two contacts are in electrically contact with a source electrode and a drain electrode of the metal-oxide-semiconductor field-effect transistor respectively.
[0098]
Accordingly, a 3D memory device and a fabricating method are disclosed. In the disclosed method, an alternating conductive/dielectric stack can include an inclined portion formed on a slope of an insulating layer. The inclined portion of the alternating conductive/dielectric stack can be used to replace the staircase structure. The contacting surfaces of the multiple conductive layers of the alternating conductive/dielectric stack can be at the inclined portion and co-planar with each other. Thus, multiple contacts can be formed in a single process to electronically contact with the multiple conductive layers. Without forming the staircase structure, multiple trim-etch processes are not necessary, the cost of multiple photoresist masks and etching processes can be saved. Moreover, the drawbacks including short problem, leakage problem and breakdown problem caused by the difficulty of controlling the staircase structure fabricating process can be avoided.
[0099]
In some embodiments, the method comprises: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.
[0100]
In some embodiments, the method further comprises: before forming the first insulating layer, forming a metal-oxide-semiconductor field-effect transistor on the substrate in the peripheral region; wherein forming the first insulating layer includes forming the first insulating layer to cover the metal-oxide-semiconductor field-effect transistor.
[0101]
In some embodiments, forming the first insulating layer comprises: forming the first insulating layer on the substrate in both the peripheral region and the core region; and removing a portion of the first insulating layer in the core region, such that the remaining portion of the first insulating layer in the peripheral region has the slope near the boundary between the peripheral region and the core region.
[0102]
In some embodiments, forming the first insulating layer comprises: forming the first insulating layer having a slope with a slant angle in a range from about 30 degrees to about 90 degrees.
[0103]
In some embodiments, forming the alternating conductive/dielectric stack comprises: forming an alternating dielectric stack on the substrate and the first insulating layer, the alternating dielectric stack including a first lateral portion on the substrate in the core region, a second lateral portion on a top surface of the first insulating layer in the peripheral region, and an inclined portion on the slope of the first insulating layer near the boundary between the peripheral region and the core region; removing the second lateral portion of the alternating dielectric stack; planarizing a top surface of the inclined portion of the alternating dielectric stack, such that the top surfaces of the first insulating layer, the inclined portion of the alternating dielectric stack, and the first lateral portion of the alternating dielectric stack are co-planar; and converting remaining portions of the alternating dielectric stack to the alternating conductive/dielectric stack.
[0104]
In some embodiments, forming the alternating dielectric stack comprises: forming at least 32 dielectric layer pairs stacked in a vertical direction above the substrate, each dielectric layer pair including a first dielectric layer and a second dielectric layer that has a material different with the first dielectric layer.
[0105]
In some embodiments, forming the alternating dielectric stack comprises: forming at least 32 dielectric layer pairs stacked in the vertical direction, each dielectric layer pair including a silicon oxide layer and a silicon nitride layer.
[0106]
In some embodiments, forming the alternating dielectric stack comprises: forming a bottom second dielectric layer on a top surface of the first insulating layer as a first chemical mechanical polishing stop layer in the peripheral region; and forming a top second dielectric layer as a second chemical mechanical polishing stop layer in the core region; wherein the first chemical mechanical polishing stop layer and the second chemical mechanical polishing stop layer are approximately co-planar.
[0107]
In some embodiments, removing the second lateral portion of the alternating dielectric stack comprises: removing the first dielectric layers and the second dielectric layers of the alternating dielectric stack in the alternating dielectric stack except the bottom second dielectric layer.
[0108]
In some embodiments, planarizing the top surface of the inclined portion of the alternating dielectric stack comprises: removing an upper portion of the inclined portion of the alternating dielectric stack that is higher than a top surface of the first chemical mechanical polishing layer or the second chemical mechanical polishing stop layer.
[0109]
In some embodiments, converting remaining portions of the alternating dielectric stack to the alternating conductive/dielectric stack comprises: replacing the second dielectric layers in the alternating dielectric stack with conductive layers.
[0110]
In some embodiments, forming the plurality of contacts comprises: forming a second insulating layer in both the peripheral region and the core region to cover a top surface of the alternating conductive/dielectric stack; and forming a plurality of contacts in the second insulating layer to electrically contact with the plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack; wherein the plurality of contacts have a same height.
[0111]
In some embodiments, forming the plurality of contacts comprises: forming a plurality of through holes in the second insulating layer in a single etching process; and depositing a conductive material into the plurality of through holes to form the plurality of contacts.
[0112]
In some embodiments, the method further comprises: forming two contacts in the first and second insulating layers to electrically contact a source electrode and a drain electrode of the metal-oxide-semiconductor field-effect transistor respectively.
[0113]
Another aspect of the present disclosure provides a three-dimensional (3D) memory device, comprising: an insulating layer on a substrate in a peripheral region, the insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; an alternating conductive/dielectric stack on the substrate and the slope of the insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the insulating layer; and a plurality of contacts in electrical contact with a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.
[0114]
The device further comprises: a metal-oxide-semiconductor field-effect transistor on the substrate in the peripheral region, wherein the insulating layer covers the metal-oxide-semiconductor field-effect transistor; and two contacts in the insulating layer and in electrical contact with a source electrode and a drain electrode of the metal-oxide-semiconductor field-effect transistor respectively.
[0115]
In some embodiments, a slant angle of the slope of the insulating layer is in a range from about 30 degrees to about 90 degrees.
[0116]
In some embodiments, the alternating conductive/dielectric stack comprises: at least 32 conductive/dielectric layer pairs, each including a dielectric layer and a conductive layer.
[0117]
In some embodiments, a top surface of the lateral portion of the alternating conductive/dielectric stack is co-planar with a top surface of the inclined portion of the alternating conductive/dielectric stack.
[0118]
In some embodiments, the plurality of contacts have a same height and are formed in a same process.
[0119]
The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the disclosure and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the disclosure and guidance .
[0120]
Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
[0121]
The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor (s) , and thus, are not intended to limit the present disclosure and the appended claims in any way.
[0122]
The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

[Claim 1]
A method for forming a three-dimensional (3D) memory device, comprising: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.
[Claim 2]
The method of claim 1, further comprising: before forming the first insulating layer, forming a metal-oxide-semiconductor field-effect transistor on the substrate in the peripheral region; wherein forming the first insulating layer includes forming the first insulating layer to cover the metal-oxide-semiconductor field-effect transistor.
[Claim 3]
The method of claim 1, wherein forming the first insulating layer comprises: forming the first insulating layer on the substrate in both the peripheral region and the core region; and removing a portion of the first insulating layer in the core region, such that the remaining portion of the first insulating layer in the peripheral region has the slope near the boundary between the peripheral region and the core region.
[Claim 4]
The method of claim 1, wherein forming the first insulating layer comprises: forming the first insulating layer having a slope with a slant angle in a range from about 30 degrees to about 90 degrees.
[Claim 5]
The method of claim 1, wherein forming the alternating conductive/dielectric stack comprises: forming an alternating dielectric stack on the substrate and the first insulating layer, the alternating dielectric stack including a first lateral portion on the substrate in the core region, a second lateral portion on a top surface of the first insulating layer in the peripheral region, and an inclined portion on the slope of the first insulating layer near the boundary between the peripheral region and the core region; removing the second lateral portion of the alternating dielectric stack; planarizing a top surface of the inclined portion of the alternating dielectric stack, such that the top surfaces of the first insulating layer, the inclined portion of the alternating dielectric stack, and the first lateral portion of the alternating dielectric stack are co-planar; and converting remaining portions of the alternating dielectric stack to the alternating conductive/dielectric stack.
[Claim 6]
The method of claim 5, wherein forming the alternating dielectric stack comprises: forming at least 32 dielectric layer pairs stacked in a vertical direction above the substrate, each dielectric layer pair including a first dielectric layer and a second dielectric layer that has a material different with the first dielectric layer.
[Claim 7]
The method of claim 6, wherein forming the alternating dielectric stack comprises: forming at least 32 dielectric layer pairs stacked in the vertical direction, each dielectric layer pair including a silicon oxide layer and a silicon nitride layer.
[Claim 8]
The method of claim 6, wherein forming the alternating dielectric stack comprises: forming a bottom second dielectric layer on a top surface of the first insulating layer as a first chemical mechanical polishing stop layer in the peripheral region; and forming a top second dielectric layer as a second chemical mechanical polishing stop layer in the core region; wherein the first chemical mechanical polishing stop layer and the second chemical mechanical polishing stop layer are approximately co-planar.
[Claim 9]
The method of claim 8, wherein removing the second lateral portion of the alternating dielectric stack comprises: removing the first dielectric layers and the second dielectric layers of the alternating dielectric stack in the alternating dielectric stack except the bottom second dielectric layer.
[Claim 10]
The method of claim 9, wherein planarizing the top surface of the inclined portion of the alternating dielectric stack comprises: removing an upper portion of the inclined portion of the alternating dielectric stack that is higher than a top surface of the first chemical mechanical polishing layer or the second chemical mechanical polishing stop layer.
[Claim 11]
The method of claim 6, wherein converting remaining portions of the alternating dielectric stack to the alternating conductive/dielectric stack comprises: replacing the second dielectric layers in the alternating dielectric stack with conductive layers.
[Claim 12]
The method of claim 1, wherein forming the plurality of contacts comprises: forming a second insulating layer in both the peripheral region and the core region to cover a top surface of the alternating conductive/dielectric stack; and forming a plurality of contacts in the second insulating layer to electrically contact with the plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack; wherein the plurality of contacts have a same height.
[Claim 13]
The method of claim 12, wherein forming the plurality of contacts comprises: forming a plurality of through holes in the second insulating layer in a single etching process; and depositing a conductive material into the plurality of through holes to form the plurality of contacts.
[Claim 14]
The method of claim 2, further comprising: forming two contacts in the first and second insulating layers to electrically contact a source electrode and a drain electrode of the metal-oxide-semiconductor field-effect transistor respectively.
[Claim 15]
A three-dimensional (3D) memory device, comprising: an insulating layer on a substrate in a peripheral region, the insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; an alternating conductive/dielectric stack on the substrate and the slope of the insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the insulating layer; and a plurality of contacts in electrical contact with a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.
[Claim 16]
The device of claim 15, further comprising: a metal-oxide-semiconductor field-effect transistor on the substrate in the peripheral region, wherein the insulating layer covers the metal-oxide-semiconductor field-effect transistor; and two contacts in the insulating layer and in electrical contact with a source electrode and a drain electrode of the metal-oxide-semiconductor field-effect transistor respectively.
[Claim 17]
The device of claim 15, wherein: a slant angle of the slope of the insulating layer is in a range from about 30 degrees to about 90 degrees.
[Claim 18]
The device of claim 15, wherein the alternating conductive/dielectric stack comprises: at least 32 conductive/dielectric layer pairs, each including a dielectric layer and a conductive layer.
[Claim 19]
The device of claim 15, wherein: a top surface of the lateral portion of the alternating conductive/dielectric stack is co-planar with a top surface of the inclined portion of the alternating conductive/dielectric stack.
[Claim 20]
The device of claim 15, wherein the plurality of contacts have a same height and are formed in a same process.

Drawings

[ Fig. 1A]  
[ Fig. 1B]  
[ Fig. 1C]  
[ Fig. 1D]  
[ Fig. 1E]  
[ Fig. 1F]  
[ Fig. 2A]  
[ Fig. 2B]  
[ Fig. 3]  
[ Fig. 4A]  
[ Fig. 4B]  
[ Fig. 4C]  
[ Fig. 4D]  
[ Fig. 4E]  
[ Fig. 4F]  
[ Fig. 4G]  
[ Fig. 4H]