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1. WO2017026321 - 多層基板、部品実装基板及び部品実装基板の製造方法

公開番号 WO/2017/026321
公開日 16.02.2017
国際出願番号 PCT/JP2016/072605
国際出願日 02.08.2016
IPC
H01L 23/12 2006.1
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
12マウント,例.分離できない絶縁基板
H01L 21/60 2006.1
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
02半導体装置またはその部品の製造または処理
04少なくとも一つの電位障壁または表面障壁,例.PN接合,空乏層,キャリア集中層,を有する装置
50サブグループH01L21/06~H01L21/326の一つに分類されない方法または装置を用いる半導体装置の組立
60動作中の装置にまたは装置から電流を流すためのリードまたは他の導電部材の取り付け
H05K 1/02 2006.1
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
1印刷回路
02細部
H05K 3/32 2006.1
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
30電気部品,例.抵抗器,を印刷回路に取り付けること
32印刷回路に対する電気部品または電線の電気的接続
CPC
H01L 21/4853
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4846Leads on or in insulating or insulated substrates, e.g. metallisation
4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
H01L 21/4857
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4846Leads on or in insulating or insulated substrates, e.g. metallisation
4857Multilayer substrates
H01L 21/486
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4846Leads on or in insulating or insulated substrates, e.g. metallisation
486Via connections through the substrate with or without pins
H01L 2224/13144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
13099Material
131with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
13138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
13144Gold [Au] as principal constituent
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/16227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
16227the bump connector connecting to a bond pad of the item
出願人
  • 株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP]/[JP]
発明者
  • 用水 邦明 YOSUI, Kuniaki
  • 池野 圭亮 IKENO, Keisuke
代理人
  • アセンド特許業務法人 ASCEND IP LAW FIRM
優先権情報
2015-15817410.08.2015JP
2015-18788925.09.2015JP
公開言語 (言語コード) 日本語 (ja)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) MULTILAYER SUBSTRATE, COMPONENT MOUNTING SUBSTRATE, METHOD FOR MANUFACTURING COMPONENT MOUNTING SUBSTRATE
(FR) SUBSTRAT MULTICOUCHE, SUBSTRAT DE MONTAGE DE COMPOSANTS, PROCÉDÉ DE FABRICATION DE SUBSTRAT DE MONTAGE DE COMPOSANTS
(JA) 多層基板、部品実装基板及び部品実装基板の製造方法
要約
(EN) To provide a multilayer substrate, a component mounting substrate, and a method for manufacturing a component mounting substrate, such that it is possible to mount components in a more reliable manner. A multilayer substrate according to the present invention is characterized in being provided with a base having a main surface, first to nth external electrodes provided on the main surface, and a first dummy layer provided in the base and not connected with other conductive bodies; and, defining a distance Dm as the distance from an mth external electrode to the external electrode closest to the mth electrode out of the first to nth external electrodes as viewed from the direction of a normal to the main surface, defining average Dave as the average of the distances D1 to Dn, and defining Am as the circular area centered on the mth external electrode and having a radius of distance Dm as viewed from the direction of a normal, the first dummy layer being provided within at least a partial area Am inside the area Am having a radius of the distance Dm larger than the average Dave as viewed from the direction of a normal.
(FR) L'invention consiste à fournir un substrat multicouche, un substrat de montage de composants, et un procédé de fabrication d'un substrat de montage de composants, de telle sorte qu'il soit possible de monter des composants de façon plus fiable. Un substrat multicouche selon la présente invention est caractérisé en ce qu'il comprend une base ayant une surface principale, des première à nième électrodes externes disposées sur la surface principale, et une première couche factice disposée dans la base et qui n'est pas connectée à d'autres corps conducteurs; et, en ce qu'il définit une distance Dm comme étant la distance entre une mième électrode externe et l'électrode externe la plus près de la mième électrode parmi les première à nième électrodes externes lorsque l'on regarde depuis la direction d'une normale à la surface principale, en ce qu'il définit une distance moyenne Dave comme étant la moyenne des distances D1 à Dn, et en ce qu'il définit Am comme étant la zone circulaire centrée sur la mième électrode externe et ayant un rayon de distance Dm lorsque l'on regarde depuis la direction d'une normale, la première couche factice étant disposée dans au moins une zone partielle Am à l'intérieur de la zone Am ayant un rayon de la distance Dm supérieur à la distance moyenne Dave lorsque l'on regarde depuis la direction d'une normale.
(JA) 実装部品をより確実に実装することができる多層基板、部品実装基板及び部品実装基板の製造方法を提供することである。 本発明に係る多層基板は、主面を有する素体と、主面に設けられ、かつ、第1の外部電極ないし第nの外部電極と、素体内に設けられ、他の導体とは接続されていない第1のダミー層と、を備えており、主面の法線方向から見たときに、第mの外部電極から第1の外部電極ないし第nの外部電極の内の第mの外部電極に最も近い外部電極までの距離を距離Dmと定義し、距離D1ないし距離Dnの平均を平均Daveと定義し、法線方向から見たときに、第mの外部電極を中心とし距離Dmを半径とする円形の領域を領域Amと定義し、第1のダミー層は、法線方向から見たときに、平均Daveよりも大きな距離Dmを半径とする領域Amの内の少なくとも一部の領域Am内に設けられていること、を特徴とする。
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