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1. WO2017009922 - 配線形成方法および配線形成装置

公開番号 WO/2017/009922
公開日 19.01.2017
国際出願番号 PCT/JP2015/070005
国際出願日 13.07.2015
IPC
H05K 3/40 2006.01
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
40印刷回路への,または印刷回路間の電気的接続のための印刷要素の形成
CPC
H01L 2224/04105
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/73267
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73251on different surfaces
73267Layer and HDI connectors
H01L 2224/83192
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
83using a layer connector
8319Arrangement of the layer connectors prior to mounting
83192wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
H01L 2224/92244
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
92Specific sequence of method steps
922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
9222Sequential connecting processes
92242the first connecting process involving a layer connector
92244the second connecting process involving a build-up interconnect
H01L 2924/15153
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
15Details of package parts other than the semiconductor or other solid state devices to be connected
151Die mounting substrate
1515Shape
15153the die mounting substrate comprising a recess for hosting the device
出願人
  • 富士機械製造株式会社 FUJI MACHINE MFG. CO., LTD. [JP]/[JP]
発明者
  • 鈴木 雅登 SUZUKI, Masato
  • 藤田 政利 FUJITA, Masatoshi
  • 橋本 良崇 HASHIMOTO, Yoshitaka
  • 川尻 明宏 KAWAJIRI, Akihiro
  • 塚田 謙磁 TSUKADA, Kenji
代理人
  • 特許業務法人ネクスト NEXT INTERNATIONAL
優先権情報
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) WIRING FORMATION METHOD AND WIRING FORMATION DEVICE
(FR) PROCÉDÉ ET DISPOSITIF DE FORMATION DE CÂBLAGE
(JA) 配線形成方法および配線形成装置
要約
(EN)
With the wiring formation device and method according to the present invention, a first wiring 150 is formed on a circuit board 70 by means of a metal-containing liquid, and a resin layer 156 having a via-hole 152 that partially exposes the wiring is formed on the circuit board. In addition, a conductive metal lump 96 is placed in the via-hole. Then, a second wiring 160 is formed on the resin layer by means of a metal-containing liquid. In such a manner, in the wiring formation method according to the present invention, the first wiring and the second wiring are electrically connected when the conductive metal lump is placed in the via-hole. On the other hand, in a conventional wiring formation method, a first wiring and a second wiring are electrically connected when a metallic thin film is laminated inside a via-hole through baking of a metal-containing liquid. Thus, with the wiring formation method according to the present invention, since it is not necessary to form a lamination of a metallic thin film, improvement in throughput is achieved and deterioration of the resin layer can be prevented.
(FR)
La présente invention concerne un dispositif et un procédé de formation de câblage qui permettent de former un premier câblage (150) sur une carte de circuits imprimés (70) au moyen d'un liquide contenant un métal et une couche de résine (156) ayant un trou d'interconnexion (152) qui fait apparaître partiellement le câblage formé sur la carte de circuits imprimés. De plus, un morceau de métal conducteur (96) est placé dans le trou d'interconnexion. Ensuite, un second câblage (160) est formé sur la couche de résine au moyen d'un liquide contenant du métal. De cette manière, selon le procédé de formation de câblage de la présente invention, le premier câblage et le second câblage sont connectés électriquement lorsque le morceau de métal conducteur est placé dans le trou d'interconnexion. Par ailleurs, selon un procédé de formation de câblage classique, un premier câblage et un second câblage sont connectés électriquement lorsqu'un film mince métallique est stratifié à l'intérieur d'un trou d'interconnexion par cuisson d'un liquide contenant du métal. Ainsi, le procédé de formation de câblage selon la présente invention, étant donné qu'il n'est pas nécessaire de former une stratification d'un film mince métallique, améliore le débit et évite de détériorer la couche de résine.
(JA)
本発明の配線形成装置および方法では、回路基板70の上に金属含有液によって第1の配線150が形成され、その配線の一部が露出するビア穴152を有する樹脂層156が、回路基板の上に形成される。また、導電性の金属塊96がビア穴に載置される。そして、樹脂層の上に、金属含有液によって第2の配線160が形成される。このように、本発明の配線形成方法では、導電性の金属塊がビア穴に載置されることで、第1の配線と第2の配線とが電気的に接続される。一方、従来の配線形成方法では、金属含有液の焼成によって、ビア穴の内部に金属製の薄膜が積層されることで、第1の配線と第2の配線とが電気的に接続される。つまり、本発明の配線形成方法によれば、金属製の薄膜を積層する必要がなくなり、スループットの向上を図るとともに、樹脂層の劣化を防止することが可能となる。
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