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1. WO2017006633 - 半導体装置および半導体装置の製造方法

公開番号 WO/2017/006633
公開日 12.01.2017
国際出願番号 PCT/JP2016/064925
国際出願日 19.05.2016
IPC
H01L 23/28 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
28封緘,例.封緘層,被覆
H01L 21/56 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
02半導体装置またはその部品の製造または処理
04少なくとも一つの電位障壁または表面障壁,例.PN接合,空乏層,キャリア集中層,を有する装置
50サブグループH01L21/06~H01L21/326の一つに分類されない方法または装置を用いる半導体装置の組立
56封緘,例.封緘層,被覆
H01L 23/00 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
CPC
H01L 21/4842
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4821Flat leads, e.g. lead frames with or without insulating supports
4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
H01L 21/561
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
561Batch processing
H01L 21/568
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
568Temporary substrate used as encapsulation process aid
H01L 2224/32245
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32245the item being metallic
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48247
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48245the item being metallic
48247connecting the wire to a bond pad of the item
出願人
  • アオイ電子株式会社 AOI ELECTRONICS CO.,LTD. [JP]/[JP] (AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BE, BF, BG, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CL, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, FR, GA, GD, GE, GH, GM, GN, GQ, GR, GT, GW, HN, HR, HU, ID, IE, IL, IN, IR, IS, IT, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MC, MD, ME, MG, MK, ML, MN, MR, MT, MW, MX, MY, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SI, SK, SL, SM, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW)
  • 三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP]/[JP]
発明者
  • 澤本 修一 SAWAMOTO, Shuichi
  • 岩部 嵩司 IWABU, Koji
  • 高尾 勝大 TAKAO, Katsuhiro
  • 平井 盟人 HIRAI, Akihito
  • 齊藤 讓一 SAITO, Joichi
代理人
  • 永井 冬紀 NAGAI, Fuyuki
優先権情報
2015-13621607.07.2015JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION D'UN DISPOSITIF SEMI-CONDUCTEUR
(JA) 半導体装置および半導体装置の製造方法
要約
(EN)
This semiconductor device is provided with: an island; a semiconductor chip that is provided on the upper surface of the island; a plurality of signal terminals that are disposed on the outer peripheral side of the semiconductor chip; a grounding terminal that is disposed on the outer peripheral side of the signal terminals; a conductive connecting member that electrically connects a plurality of electrodes of the semiconductor chip and the signal terminals to each other, respectively; a sealing resin that seals the island, semiconductor chip, conductive connecting member, signal terminals, and grounding terminal such that the lower surface of the island, the lower surfaces of the signal terminals, and the lower surface of the grounding terminal are exposed to the outside; and a shield metal film that is attached to the outer peripheral-side surface and the upper surface of the sealing resin, and to a part of the grounding terminal.
(FR)
La présente invention concerne un dispositif semi-conducteur qui comporte : un îlot; une puce semi-conductrice qui est disposée sur la surface supérieure de l'îlot; une pluralité de bornes de signaux qui sont disposées du côté de la périphérie extérieure de la puce semi-conductrice; une borne de masse qui est disposée du côté de la périphérie extérieure des bornes de signaux; un organe connecteur conducteur qui connecte électriquement entre elles une pluralité d'électrodes de la puce semi-conductrice et les bornes de signaux, respectivement; une résine d'étanchéité qui scelle l'îlot, la puce semi-conductrice, l'organe connecteur conducteur, les bornes de signaux, et la borne de masse de sorte que la surface inférieure de l'îlot, les surfaces inférieures des bornes de signaux, et la surface inférieure de la borne de masse soient exposées à l'extérieur; et une pellicule de métal de blindage qui est fixée à la surface du côté de la périphérie extérieure et à la surface supérieure de la résine d'étanchéité, et à une partie de la borne de masse.
(JA)
半導体装置は、アイランドと、前記アイランドの上面に設けられる半導体チップと、前記半導体チップの外周側に配置された複数の信号端子と、前記複数の信号端子の外周側に配置された接地用端子と、前記半導体チップの複数の電極の各々と前記複数の信号端子の各々とを電気的に接続する導電性接続部材と、前記アイランドの下面、前記複数の信号端子の下面および前記接地用端子の下面が外部に露出するように、前記アイランドと、前記半導体チップと、前記導電性接続部材と、前記複数の信号端子と、前記接地用端子とを封止する封止樹脂と、前記封止樹脂の外周側面および上面と、前記接地用端子の一部とに膜付けされたシールド金属膜とを備える。
他の公開
GB1800780.7
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