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1. WO2015025347 - 電子回路基板、それを用いた半導体装置及びその製造方法

公開番号 WO/2015/025347
公開日 26.02.2015
国際出願番号 PCT/JP2013/072044
国際出願日 19.08.2013
IPC
H01L 23/15 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
12マウント,例.分離できない絶縁基板
14材料またはその電気特性に特徴のあるもの
15セラミックまたはガラス基板
CPC
H01L 21/4846
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4846Leads on or in insulating or insulated substrates, e.g. metallisation
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48225the item being non-metallic, e.g. insulating substrate with or without metallisation
48227connecting the wire to a bond pad of the item
H01L 2224/48472
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
484Connecting portions
4847the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
48472the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
H01L 2224/73265
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73251on different surfaces
73265Layer and wire connectors
出願人
  • 株式会社日立製作所 HITACHI, LTD. [JP/JP]; 東京都千代田区丸の内一丁目6番6号 6-6, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1008280, JP
発明者
  • 直江 和明 NAOE, Kazuaki; JP
  • 天明 浩之 TENMEI, Hiroyuki; JP
  • 西亀 正志 NISHIKI, Masashi; JP
代理人
  • 井上 学 INOUE, Manabu; 東京都千代田区丸の内一丁目6番1号 株式会社日立製作所内 c/o HITACHI, LTD., 6-1, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1008220, JP
優先権情報
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) ELECTRONIC CIRCUIT BOARD, SEMICONDUCTOR DEVICE USING SAME, AND MANUFACTURING METHOD FOR SAME
(FR) SUBSTRAT DE CIRCUIT ÉLECTRONIQUE, DISPOSITIF À SEMI-CONDUCTEURS METTANT EN ŒUVRE CE SUBSTRAT, ET PROCÉDÉ DE FABRICATION DE CE SUBSTRAT
(JA) 電子回路基板、それを用いた半導体装置及びその製造方法
要約
(EN)
The purpose of the present invention is to provide an electronic circuit board for which volume resistivity of a ceramic substrate fabricated using an aerosol deposition method is increased, and insulation reliability is improved, as well as a semiconductor device using same and a manufacturing method for same. The present invention provides an electronic circuit board characterized in being provided with a metal material and an insulating layer formed on the surface of the metal material and comprising inorganic material containing grain sizes of 10 to 20 nm, and characterized in that the insulating layer is such that moisture content contained therein is less than 0.08 g/cm3. In addition, the present invention provides a manufacturing method for the electronic circuit board that is characterized in projecting an aerosol containing particles constituting an insulating layer onto the metal material so as to form the insulating layer, and heating either the surface of the metal material or the surface of the insulating layer.
(FR)
L'invention a pour objectif de fournir un substrat de circuit électronique, un dispositif à semi-conducteurs mettant en œuvre ce substrat, et un procédé de fabrication de ce substrat tels que la résistivité transversale d'un substrat céramique confectionné par dépôt d'aérosol, est augmentée, et la fiabilité est améliorée. Plus précisément, l'invention fournit un substrat de circuit électronique qui est caractéristique en ce qu'il est équipé : d'un matériau métallique ; et d'une couche isolante formée à la surface dudit matériau métallique, constituée d'un matériau inorganique de diamètre de grains cristallins compris entre 10 et 20nm, et dont comprenant une quantité d'eau inférieure à 0,08g/cm3. Enfin, l'invention fournit un procédé de fabrication de substrat de circuit électronique qui est caractéristique en ce que la couche isolante est formée sur le matériau métallique par projection sur le matériau métallique d'un aérosol contenant des particules destinées à configurer la couche isolante, et la surface dudit matériau métallique ou la surface de la couche isolante est chauffée.
(JA)
 本発明は、エアロゾルデポジション法で作製したセラミック基板の体積抵抗率を増加させ、絶縁信頼性が向上した電子回路基板、それを用いた半導体装置及びその製造方法を提供することを目的とする。 本発明は、金属材料と、前記金属材料の表面に形成された10~20nmの結晶粒径を含む無機材料からなる絶縁層とを備え、前記絶縁層は、含有する水分量が0.08g/cm未満であることを特徴とする電子回路基板を提供する。また、本発明は、絶縁層を構成する粒子を含むエアロゾルを金属材料に噴射して金属材料に絶縁層を形成し、前記金属材料表面または前記絶縁層表面のいずれかを加熱することを特徴とする電子回路基板の製造方法を提供する。
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