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1. WO2015019444 - 半導体装置の製造方法、及び、半導体装置

公開番号 WO/2015/019444
公開日 12.02.2015
国際出願番号 PCT/JP2013/071355
国際出願日 07.08.2013
IPC
H01L 21/336 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
02半導体装置またはその部品の製造または処理
04少なくとも一つの電位障壁または表面障壁,例.PN接合,空乏層,キャリア集中層,を有する装置
18不純物,例.ドーピング材料,を含むまたは含まない周期表第IV族の元素またはA↓I↓I↓IB↓V化合物から成る半導体本体を有する装置
334ユニポーラ型の装置の製造のための多段階工程
335電界効果トランジスタ
336絶縁ゲートを有するもの
H01L 29/78 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
29整流,増幅,発振またはスイッチングに特に適用される半導体装置であり,少なくとも1つの電位障壁または表面障壁を有するもの;少なくとも1つの電位障壁または表面障壁,例.PN接合空乏層またはキャリア集中層,を有するコンデンサーまたは抵抗器;半導体本体または電極の細部
66半導体装置の型
68整流,増幅またはスイッチされる電流を流さない電極に電流のみまたは電位のみを与えることにより制御できるもの
76ユニポーラ装置
772電界効果トランジスタ
78絶縁ゲートによって生じる電界効果を有するもの
CPC
H01L 2029/42388
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
4232with insulated gate
42384for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
42388characterised by the shape of the insulating material
H01L 21/823487
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
823487with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
H01L 29/42356
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
4232with insulated gate
42356Disposition, e.g. buried gate electrode
H01L 29/42392
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
4232with insulated gate
42384for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
42392fully surrounding the channel, e.g. gate-all-around
H01L 29/66545
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
66545using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
H01L 29/66666
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
66666Vertical transistors
出願人
  • ユニサンティス エレクトロニクス シンガポール プライベート リミテッド UNISANTIS ELECTRONICS SINGAPORE PTE. LTD. [SG/SG]; ノースブリッジロード 111、ペニンシュラ プラザ #16-04 111, North Bridge Road, #16-04, Peninsula Plaza 179098, SG (AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BE, BF, BG, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CL, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GT, GW, HN, HR, HU, ID, IE, IL, IN, IS, IT, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MC, MD, ME, MG, MK, ML, MN, MR, MT, MW, MX, MY, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SI, SK, SL, SM, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, ZA, ZM, ZW)
  • 舛岡 富士雄 MASUOKA Fujio [JP/JP]; JP (US)
  • 中村 広記 NAKAMURA Hiroki [JP/JP]; JP (US)
発明者
  • 舛岡 富士雄 MASUOKA Fujio; JP
  • 中村 広記 NAKAMURA Hiroki; JP
代理人
  • 辻居 幸一 TSUJII Koichi; 東京都千代田区丸の内3丁目3番1号 新東京ビル 中村合同特許法律事務所 NAKAMURA & PARTNERS, Shin-Tokyo Bldg., 3-1, Marunouchi 3-chome, Chiyoda-ku, Tokyo 1008355, JP
優先権情報
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEUR ET DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置の製造方法、及び、半導体装置
要約
(EN)
Provided is a manufacturing method, i.e., a gate-last process, wherein a gate electrode and gate wiring are formed at the periphery of a first columnar semiconductor layer, and at the same time, a contact electrode and contact wiring, which are connected to a fin-like semiconductor layer upper portion, are formed at the periphery of a second columnar semiconductor layer, said method being provided for the purpose of manufacturing a surrounding gate transistor (SGT) having a structure for functioning, by means of self-alignment, the columnar semiconductor layer upper portion as an n-type semiconductor layer or a p-type semiconductor layer due to a work function difference between a metal and a semiconductor. A contact structure and a structure of the SGT obtained as results of the manufacturing method are also provided.
(FR)
La présente invention concerne un procédé de fabrication, c'est-à-dire un processus "grille en dernier", au cours duquel une électrode grille et un câblage de grille sont formés à la périphérie d'une première couche semi-conductrice en colonne, et au cours duquel une électrode de contact et un câblage de contact, qui sont connectés à une partie supérieure de couche semi-conductrice en forme d'ailette, sont formés en même temps à la périphérie d'une seconde couche semi-conductrice en colonne, ledit procédé visant à fabriquer un transistor à grille enveloppante (SGT) qui possède une structure où, à l'aide d'un auto-alignement, la partie supérieure de couche semi-conductrice en colonne fait office de couche semi-conductrice du type n ou de couche semi-conductrice du type p en raison d'une différence de travail d'extraction entre un métal et un semi-conducteur. La présente invention se rapporte également à une structure de contact et à une structure du SGT qui sont obtenues grâce au procédé de fabrication.
(JA)
 第1の柱状半導体層の周囲にゲート電極及びゲート配線を形成し、同時に第2の柱状半導体層の周囲にフィン状半導体層上部と接続するコンタクト電極及びコンタクト配線を形成するゲートラストプロセスであって、さらに自己整合で柱状半導体層上部を金属と半導体との仕事関数差によってn型半導体層もしくはp型半導体層として機能させる構造を持つSGTの製造方法と、その結果得られるコンタクト構造とSGTの構造を提供する。
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