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1. WO2015016289 - 配線基板および電子装置

公開番号 WO/2015/016289
公開日 05.02.2015
国際出願番号 PCT/JP2014/070141
国際出願日 30.07.2014
IPC
H05K 3/34 2006.01
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
30電気部品,例.抵抗器,を印刷回路に取り付けること
32印刷回路に対する電気部品または電線の電気的接続
34ハンダ付けによるもの
H01L 23/12 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
12マウント,例.分離できない絶縁基板
CPC
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48137
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
48137the bodies being arranged next to each other, e.g. on a common substrate
H01L 2224/73265
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73251on different surfaces
73265Layer and wire connectors
H01L 2224/83385
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
83using a layer connector
8338Bonding interfaces outside the semiconductor or solid-state body
83385Shape, e.g. interlocking features
H01L 23/13
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
13characterised by the shape
H01L 23/24
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
16Fillings or auxiliary members in containers ; or encapsulations; , e.g. centering rings
18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
24solid or gel at the normal operating temperature of the device
出願人
  • 京セラ株式会社 KYOCERA CORPORATION [JP/JP]; 京都府京都市伏見区竹田鳥羽殿町6番地 6, Takeda Tobadono-cho, Fushimi-ku, Kyoto-shi, Kyoto 6128501, JP
発明者
  • 川崎 晃一 KAWASAKI,Kouichi; JP
優先権情報
2013-15786230.07.2013JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) WIRING BASE PLATE AND ELECTRONIC DEVICE
(FR) PLAQUE DE BASE DE CÂBLAGE ET DISPOSITIF ÉLECTRONIQUE
(JA) 配線基板および電子装置
要約
(EN)
[Problem] To reduce the possibility for a void to appear inside a joining material when joining an electronic component to an electrode. [Solution] A wiring base plate (1) has an insulation base plate (11), and a plurality of electrodes (12) provided side-by-side in planar view on the insulation base plate (11), the electrodes (12) having an opening (12b) in the outer periphery and a slit (12a) oriented from the outer periphery to the interior, and, among two electrodes (12) next to each other, the slit (12a) in one electrode (12) having, intersecting the outer periphery of the other electrode (12), a central line (12c) tracing to the slit (12a).
(FR)
Le problème décrit par la présente invention est de réduire la possibilité qu'un vide apparaisse à l'intérieur d'un matériau d'assemblage lors de l'assemblage d'un composant électronique à une électrode. Selon la solution de la présente invention, une plaque de base de câblage (1) comprend une plaque de base isolante (11), et une pluralité d'électrodes (12) placées côte à côte en vue plane sur la plaque de base isolante (11), les électrodes (12) comportant une ouverture (12b) dans la périphérie extérieure et une fente (12a) orientée de la périphérie extérieure vers l'intérieur, et, parmi deux électrodes (12) voisines l'une de l'autre, la fente (12a) dans une électrode (12) ayant, croisant la périphérie extérieure de l'autre électrode (12), une ligne centrale (12c) menant à la fente (12a).
(JA)
【課題】 電極上に電子部品を接合する際に、接合材内にボイドが発生する可能性を低減すること。 【解決手段】 配線基板1は、絶縁基板11と、絶縁基板11上に平面視で隣り合うようにして複数設けられた電極12とを有しており、電極12は外周縁に開口部12bを有して外周縁から内側に向かうスリット12aを有し、隣り合う2つの電極12のうち、一方の電極12にあるスリット12aは、スリット12aに引いた中心線12cが他方の電極12の外周縁と交わっている。
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